公开(公告)号：US20150256178A1

公开(公告)日：2015-09-10

申请号：US14641482

申请日：2015-03-09

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Dmitry Belousov ,  Slavik Liman ,  Nimrod Wald ,  Guy Satat

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/08

CPC classification number: H03K19/00346 ,  H03K19/0021 ,  H03K19/02 ,  H03K19/0813 ,  H03K19/177

Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

Abstract translation: 根据本发明的实施例，提供了一种装置和方法。 该装置可以包括纯粹的忆阻逻辑门，其中纯忆忆性逻辑门基本上由至少一个输入忆阻器件和输出忆阻器件组成，该器件与至少一个忆阻器件耦接并不同; 其中纯粹的忆阻器由单个控制电压控制。

公开(公告)号：US20180367149A1

公开(公告)日：2018-12-20

申请号：US15622090

申请日：2017-06-14

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Dmitry Belousov ,  Slavik Liman ,  Nimrod Wald ,  Guy Satat

IPC: H03K19/20 ,  G11C13/00

CPC classification number: H03K19/20 ,  G11C13/0002 ,  G11C13/0069

Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

公开(公告)号：US10284203B2

公开(公告)日：2019-05-07

申请号：US15622090

申请日：2017-06-14

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Dmitry Belousov ,  Slavik Liman ,  Nimrod Wald ,  Guy Satat

IPC: H03K19/20 ,  G11C13/00

Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

公开(公告)号：US09685954B2

公开(公告)日：2017-06-20

申请号：US14641482

申请日：2015-03-09

Applicant: Technion Research and Development Foundation LTD.

Inventor： Shahar Kvatinsky ,  Dmitry Belousov ,  Slavik Liman ,  Nimrod Wald ,  Guy Satat

IPC: H03K19/173 ,  H03K19/003 ,  H03K19/08 ,  H03K19/00

CPC classification number: H03K19/00346 ,  H03K19/0021 ,  H03K19/02 ,  H03K19/0813 ,  H03K19/177

Abstract: According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.