公开(公告)号：US11940483B2

公开(公告)日：2024-03-26

申请号：US17470424

申请日：2021-09-09

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G01R31/28 ,  G01R31/317 ,  G06F11/273 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F30/398 ,  H04L43/50

CPC classification number: G01R31/2815 ,  G01R31/2808 ,  G01R31/2818

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.