公开(公告)号：US11940483B2

公开(公告)日：2024-03-26

申请号：US17470424

申请日：2021-09-09

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G01R31/28 ,  G01R31/317 ,  G06F11/273 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F30/398 ,  H04L43/50

CPC classification number: G01R31/2815 ,  G01R31/2808 ,  G01R31/2818

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US11782809B2

公开(公告)日：2023-10-10

申请号：US17359261

申请日：2021-06-25

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L. Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G06F11/26 ,  G06F11/24

CPC classification number: G06F11/26 ,  G06F11/24

Abstract: A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

公开(公告)号：US20200249275A1

公开(公告)日：2020-08-06

申请号：US16778262

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G01R31/317 ,  G06F13/40

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US12061232B2

公开(公告)日：2024-08-13

申请号：US17402382

申请日：2021-08-13

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L. Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G01R31/317 ,  G01R31/01 ,  G06F11/273

CPC classification number: G01R31/31715 ,  G01R31/01 ,  G01R31/31713 ,  G06F11/2733

Abstract: A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

公开(公告)号：US20220163588A1

公开(公告)日：2022-05-26

申请号：US17534409

申请日：2021-11-23

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Sam J. Strickling

IPC: G01R31/3183 ,  G01R31/3181 ,  G01R31/3185

Abstract: A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

公开(公告)号：US20210406144A1

公开(公告)日：2021-12-30

申请号：US17359261

申请日：2021-06-25

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L. Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G06F11/26 ,  G06F11/24

Abstract: A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

公开(公告)号：US20210405108A1

公开(公告)日：2021-12-30

申请号：US17470424

申请日：2021-09-09

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L. Baldwin ,  Jonathan San ,  Lin-Yung Chen

IPC: G01R31/28

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US20200250368A1

公开(公告)日：2020-08-06

申请号：US16778249

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G06F30/398 ,  G06F13/42 ,  G06F13/20 ,  G06F115/12

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US12055584B2

公开(公告)日：2024-08-06

申请号：US17534409

申请日：2021-11-23

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Sam J. Strickling

IPC: G01R31/3183 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3181 ,  G01R31/3185 ,  G06F30/367 ,  G06F115/12 ,  G06F119/06 ,  G06F119/12

CPC classification number: G01R31/31707 ,  G01R31/30 ,  G01R31/31813 ,  G01R31/318314 ,  G01R31/318385 ,  G01R31/318572 ,  G06F30/367 ,  G06F2115/12 ,  G06F2119/06 ,  G06F2119/12

Abstract: A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

公开(公告)号：US11927627B2

公开(公告)日：2024-03-12

申请号：US17534404

申请日：2021-11-23

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Sam J. Strickling

IPC: G06F30/367 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G06F115/12 ,  G06F119/06 ,  G06F119/12

CPC classification number: G01R31/31707 ,  G01R31/30 ,  G01R31/31813 ,  G01R31/318314 ,  G01R31/318385 ,  G01R31/318572 ,  G06F30/367 ,  G06F2115/12 ,  G06F2119/06 ,  G06F2119/12

Abstract: A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.