公开(公告)号：US06256755B1

公开(公告)日：2001-07-03

申请号：US09174789

申请日：1998-10-19

申请人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

发明人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

IPC分类号： G11C2900

CPC分类号： G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

摘要： An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

摘要翻译： 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

公开(公告)号：US06544874B2

公开(公告)日：2003-04-08

申请号：US09928759

申请日：2001-08-13

申请人： Jack A. Mandelman ,  Kevin K. Chan ,  Bomy A. Chen ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Victor Ku ,  Chung H. Lam ,  Nivo Rovedo

发明人： Jack A. Mandelman ,  Kevin K. Chan ,  Bomy A. Chen ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Victor Ku ,  Chung H. Lam ,  Nivo Rovedo

IPC分类号： H01L213205

CPC分类号： H01L21/823481 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

摘要翻译： 提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。 在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。 在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

公开(公告)号：US06391703B1

公开(公告)日：2002-05-21

申请号：US09894336

申请日：2001-06-28

申请人： Nivo Rovedo ,  Chung H. Lam ,  Rebecca D. Mih

发明人： Nivo Rovedo ,  Chung H. Lam ,  Rebecca D. Mih

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.

摘要翻译： 包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及将逻辑晶体管源极和漏极与衬底隔离的埋入介质层来实现工艺集成。

公开(公告)号：US5541130A

公开(公告)日：1996-07-30

申请号：US477791

申请日：1995-06-07

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

摘要翻译： 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：US5654917A

公开(公告)日：1997-08-05

申请号：US645680

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

公开(公告)号：US5681770A

公开(公告)日：1997-10-28

申请号：US645726

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

公开(公告)号：US5672892A

公开(公告)日：1997-09-30

申请号：US645827

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

摘要翻译： 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：US20100059764A1

公开(公告)日：2010-03-11

申请号：US12618152

申请日：2009-11-13

申请人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

发明人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC分类号： H01L29/78 ,  H01L29/24

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

摘要翻译： 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07618866B2

公开(公告)日：2009-11-17

申请号：US11423227

申请日：2006-06-09

申请人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

发明人： Zhijiong Luo ,  Ricky S. Amos ,  Nivo Rovedo ,  Henry K. Utomo

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636

摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

摘要翻译： 提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。 本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。 本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。 第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除 或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

公开(公告)号：US07442619B2

公开(公告)日：2008-10-28

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L21/283 ,  H01L23/482

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。