公开(公告)号：US11676854B2

公开(公告)日：2023-06-13

申请号：US17215314

申请日：2021-03-29

申请人： Tessera LLC

发明人： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5283

摘要： A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US11804405B2

公开(公告)日：2023-10-31

申请号：US17556382

申请日：2021-12-20

申请人： Tessera LLC

发明人： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20240096693A1

公开(公告)日：2024-03-21

申请号：US18139199

申请日：2023-04-25

申请人： TESSERA LLC

发明人： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5283

摘要： A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.