公开(公告)号：US11538720B2

公开(公告)日：2022-12-27

申请号：US16932362

申请日：2020-07-17

申请人： TESSERA LLC

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John Zhang

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/423 ,  H01L21/02 ,  H01L29/786 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775 ,  H01L27/088

摘要： A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

公开(公告)号：US20220336643A1

公开(公告)日：2022-10-20

申请号：US17847448

申请日：2022-06-23

申请人： Tessera LLC

发明人： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/22 ,  H01L21/225 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L29/417 ,  H01L21/762

摘要： A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

公开(公告)号：US11380583B2

公开(公告)日：2022-07-05

申请号：US17181399

申请日：2021-02-22

申请人： TESSERA LLC

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

摘要： A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US11615988B2

公开(公告)日：2023-03-28

申请号：US17482903

申请日：2021-09-23

申请人： Tessera LLC

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L21/306 ,  H01L21/324

摘要： FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US20220344211A1

公开(公告)日：2022-10-27

申请号：US17750953

申请日：2022-05-23

申请人： TESSERA LLC

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78

摘要： An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

公开(公告)号：US20220320316A1

公开(公告)日：2022-10-06

申请号：US17726766

申请日：2022-04-22

申请人： TESSERA LLC

发明人： Michael A. Guillorn ,  Terence B. Hook ,  Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/10

摘要： A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

公开(公告)号：US11424211B2

公开(公告)日：2022-08-23

申请号：US17086785

申请日：2020-11-02

申请人： TESSERA LLC

发明人： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC分类号： H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538

摘要： Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US20220262636A1

公开(公告)日：2022-08-18

申请号：US17688068

申请日：2022-03-07

申请人： TESSERA LLC

发明人： John Christopher Arnold ,  Sean D. Burns ,  Yann Alain Marcel Mignot ,  Yongan Xu

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/02

摘要： Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

公开(公告)号：US11587830B2

公开(公告)日：2023-02-21

申请号：US17007779

申请日：2020-08-31

申请人： TESSERA LLC

发明人： Benjamin D. Briggs ,  Elbert Huang ,  Takeshi Nogami ,  Christopher J. Penny

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/3115 ,  H01L23/532 ,  H01L23/522

摘要： An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

公开(公告)号：US11557589B2

公开(公告)日：2023-01-17

申请号：US16834548

申请日：2020-03-30

申请人： TESSERA LLC

发明人： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC分类号： H01L21/76 ,  H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

摘要： A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.