公开(公告)号：US11676854B2

公开(公告)日：2023-06-13

申请号：US17215314

申请日：2021-03-29

申请人： Tessera LLC

发明人： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5283

摘要： A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US11538720B2

公开(公告)日：2022-12-27

申请号：US16932362

申请日：2020-07-17

申请人： TESSERA LLC

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John Zhang

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/423 ,  H01L21/02 ,  H01L29/786 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775 ,  H01L27/088

摘要： A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

公开(公告)号：US11380583B2

公开(公告)日：2022-07-05

申请号：US17181399

申请日：2021-02-22

申请人： TESSERA LLC

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

摘要： A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US20220406658A1

公开(公告)日：2022-12-22

申请号：US17833366

申请日：2022-06-06

申请人： Tessera LLC

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

摘要： A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US12106963B2

公开(公告)日：2024-10-01

申请号：US18140425

申请日：2023-04-27

申请人： Tessera LLC

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/027 ,  H01L21/28 ,  H01L21/31 ,  H10K71/20 ,  H10N70/00

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/76897 ,  H01L2224/0362 ,  H01L2224/11622 ,  H10K71/233 ,  H10N70/063

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US20240096627A1

公开(公告)日：2024-03-21

申请号：US18140425

申请日：2023-04-27

申请人： Tessera LLC

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/31 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US20230298941A1

公开(公告)日：2023-09-21

申请号：US17979345

申请日：2022-11-02

申请人： TESSERA LLC

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John Zhang

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/423 ,  H01L21/02 ,  H01L29/786 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775 ,  H01L27/088

CPC分类号： H01L21/823418 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696

摘要： A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

公开(公告)号：US11670510B2

公开(公告)日：2023-06-06

申请号：US17328569

申请日：2021-05-24

申请人： Tessera LLC

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/31 ,  H01L21/027 ,  H01L45/00 ,  H01L21/28 ,  H01L51/00

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/76897 ,  H01L45/1675 ,  H01L51/0018 ,  H01L2224/0362 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US20240096693A1

公开(公告)日：2024-03-21

申请号：US18139199

申请日：2023-04-25

申请人： TESSERA LLC

发明人： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5283

摘要： A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US11574864B2

公开(公告)日：2023-02-07

申请号：US17341112

申请日：2021-06-07

申请人： Tessera LLC

发明人： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.