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公开(公告)号：US06600492B1
公开(公告)日：2003-07-29
申请号：US09292375
申请日：1999-04-15
申请人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
发明人： Tetsuya Shimomura , Shigeru Matsuo , Kazuyoshi Koga , Koyo Katsura , Yasuhiro Nakatsuka , Kazushige Yamagishi
IPC分类号： G06T1500
CPC分类号： G06T1/60
摘要： In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.
摘要翻译： 为了确保在规定时间内需要总是完成处理的多个电路，例如CPU I / F电路，再现电路，视频输入电路和显示电路，都能确保能力 为了在规定的时间内对存储器进行尽可能多的访问以完成处理，有必要通过使用总线控制电路来通过内部总线来仲裁访问存储器的争用，其中优先级分配给 通过比较电路之间的访问紧急程度来动态地改变访问内部总线的电路。 以这种方式，每个必须总是在规定时间内完成它们的处理的电路确保了即使存在多个这样的电路，也可以在规定的时间内完成处理所需的存储器的访问的能力。
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公开(公告)号：US07602389B2
公开(公告)日：2009-10-13
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06T15/30
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
摘要翻译： 一种数据处理系统，包括：存储器控制器; 以及连接到所述存储器控制器的存储器; 其中所述存储器控制器包括一个渲染电路，从而根据在CPU中处理程序后提供的图形数据执行一个生成显示数据的渲染命令，并将所述显示数据存储在所述存储器中。
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3.发明授权Graphics processor and system for determining colors of the vertices of a figure 失效用于确定图形顶点颜色的图形处理器和系统公开(公告)号：US06756981B2
公开(公告)日：2004-06-29
申请号：US10223600
申请日：2002-08-20
申请人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
发明人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
IPC分类号： G06T1500
CPC分类号： G06T15/506 , G06T15/50
摘要： A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.
摘要翻译： 图形处理器包括：保持光源数据的光源表; 转换单元，用于将在光源表中设置的光源数据从浮点型（单精度浮点实数型）转换成int型（整数型）; 内积计算单元，用于基于光源数据计算顶点的法线方向，光源方向和视线方向的内积; 以及颜色计算单元，用于基于所计算的内积执行光源计算，以确定顶点的颜色。
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公开(公告)号：US06377267B1
公开(公告)日：2002-04-23
申请号：US09593496
申请日：2000-06-14
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F1300
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US06222563B1
公开(公告)日：2001-04-24
申请号：US09327355
申请日：1999-06-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F15167
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US20060203000A1
公开(公告)日：2006-09-14
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
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公开(公告)号：US07019751B2
公开(公告)日：2006-03-28
申请号：US10636769
申请日：2003-08-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，并且缓冲装置用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US5940087A
公开(公告)日：1999-08-17
申请号：US739457
申请日：1996-10-29
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
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公开(公告)号：US5581796A
公开(公告)日：1996-12-03
申请号：US164776
申请日：1993-12-10
申请人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
发明人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
摘要： In a case where a graphic image segment of which positional information is defined in a world coordinate system and of which size information is defined in a device coordinate system is developed to be displayed on a multi-window screen, the development processing performance is improved in peripheral portions of the window. A rectangular development area (first development area) associated with the window is expanded with consideration of a size information of a graphic segment so as to obtain a second development area. The second development area is compared with a rectangular area (an existence area) circumscribing a graphic image represented only with positional information of the graphic segment. As a result, whether or not the graphic segment is to be developed is determined. The first development area is reduced with consideration of size information of the graphic segment to produce a third development area. The third development area is compared with the existence area to decide whether or not the clipping operation is necessary for the graphic segment.
摘要翻译： 在世界坐标系中定义哪个位置信息的图形图像段并且在设备坐标系中定义尺寸信息的情况下，显示在多窗口屏幕上，显影处理性能得到改善 窗口的周边部分。 考虑到图形段的尺寸信息来扩展与窗口相关联的矩形显影区域（第一显影区域），以获得第二显影区域。 将第二开发区域与限定仅由图形段的位置信息表示的图形图像的矩形区域（存在区域）进行比较。 结果，确定图形片段是否被开发。 考虑到图形部分的尺寸信息，第一个开发区域减少，以产生第三个开发区域。 将第三开发区域与存在区域进行比较，以确定剪切操作是否对于图形段是必需的。
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公开(公告)号：US06704019B2
公开(公告)日：2004-03-09
申请号：US10123136
申请日：2002-04-17
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G539
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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