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公开(公告)号：US20060033583A1
公开(公告)日：2006-02-16
申请号：US11196512
申请日：2005-08-04
IPC分类号： H03L7/00
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译： 提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。 频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路 时钟生成电路，生成锁存时钟ZCLK。 复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。 锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。
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公开(公告)号：US07199676B2
公开(公告)日：2007-04-03
申请号：US11196512
申请日：2005-08-04
IPC分类号： H03K3/02
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译： 提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。 频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路 时钟生成电路，生成锁存时钟ZCLK。 复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。 锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。
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公开(公告)号：US08018445B2
公开(公告)日：2011-09-13
申请号：US11542640
申请日：2006-10-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
CPC分类号： G11C7/02 , G11C7/1036 , G11C7/1078 , G11C7/1087
摘要： Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT08, BIT16 and BIT24 when the counted number of the clock pulses of the clock SCL reaches each of count numbers 8, 16 and 24 respectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT08, BIP16 and BIT24 respectively.
摘要翻译： 抑制串行数据输入系统的功耗增加和电源噪声增加，同时更容易防止时钟偏移。 本发明的串行数据输入系统包括一个移位寄存器，其与时钟SCL同步地接收和移位串行传送的显示数据，时钟计数器对时钟SCL的时钟脉冲数进行计数，并输出每个时钟计数信号BIT08 ，BIT16和BIT24，当时钟SCL的时钟脉冲的计数数量分别达到计数数8,16和24的每一个时，并且寄存到每个存储在移位寄存器中的数据被共同并且并行存储 分别响应于每个时钟计数信号BIT08，BIP16和BIT24。
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公开(公告)号：US08238385B2
公开(公告)日：2012-08-07
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/04
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译： 一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。
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公开(公告)号：US20080019400A1
公开(公告)日：2008-01-24
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译： 一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。
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公开(公告)号：US07724060B2
公开(公告)日：2010-05-25
申请号：US11736913
申请日：2007-04-18
CPC分类号： G06F1/04
摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
摘要翻译： 一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据 逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。
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公开(公告)号：US07379036B2
公开(公告)日：2008-05-27
申请号：US10808589
申请日：2004-03-25
申请人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
发明人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
IPC分类号： G09G3/22
CPC分类号： G09G3/22 , G09G2330/08
摘要： A driving circuit for a vacuum fluorescent display for pulse-driving a filament of the vacuum fluorescent display with a pulse voltage. The driving circuit comprises a detecting unit for detecting that the level of the pulse voltage is fixed, and outputs a detection signal indicative of the result of the detection. Preferably, the driving circuit comprises a control unit for controlling at least one output of the outputs of the filament driving unit, the grid driving unit and the segment driving unit in order to terminate the driving of at least one of the filament, the grid electrode and the segment electrode, based on the detection signal.
摘要翻译： 一种用于以脉冲电压脉冲驱动真空荧光显示器的灯丝的真空荧光显示器的驱动电路。 驱动电路包括用于检测脉冲电压的电平是固定的检测单元，并且输出表示检测结果的检测信号。 优选地，驱动电路包括用于控制灯丝驱动单元，电网驱动单元和段驱动单元的输出的至少一个输出的控制单元，以便终止至少一个灯丝，栅极 和段电极，基于检测信号。
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公开(公告)号：US07400307B2
公开(公告)日：2008-07-15
申请号：US10808586
申请日：2004-03-25
申请人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
发明人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
IPC分类号： G09G3/22
CPC分类号： H03M1/005 , G09G3/2007 , G09G3/2014 , G09G3/2077 , G09G3/22 , G09G2310/027 , H03M1/822 , H03M1/86
摘要： A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, the driving circuit comprising a filament driving unit for driving the filament; a grid driving unit for pulse-driving the grid electrode; and a segment driving unit for pulse-driving the segment electrode, wherein the driving circuit comprises a controlling unit for validating or invalidating the output of the filament driving unit at a proper timing.
摘要翻译： 一种用于真空荧光显示器的驱动电路，其具有灯丝，栅电极和段电极，所述驱动电路包括用于驱动灯丝的灯丝驱动单元; 栅格驱动单元，用于脉冲驱动栅电极; 以及用于脉冲驱动所述分段电极的分段驱动单元，其中所述驱动电路包括用于在适当的定时使所述细丝驱动单元的输出有效或无效的控制单元。
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公开(公告)号：US07312769B2
公开(公告)日：2007-12-25
申请号：US10808588
申请日：2004-03-25
申请人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
发明人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
IPC分类号： G09G3/22
CPC分类号： G09G3/06 , G09G3/2014
摘要： A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, comprising a grid driving unit for pulse-driving the grid electrode, a segment driving unit for pulse-driving the segment electrode, a first controlling unit for rendering adjustable the duty ratio of the output of the grid driving unit, a second controlling unit for rendering adjustable the duty ratio of the output of the segment driving unit, and a selecting unit for selecting the first controlling unit and/or the second controlling unit.
摘要翻译： 一种具有灯丝，栅电极和段电极的真空荧光显示器的驱动电路，包括用于脉冲驱动栅电极的栅极驱动单元，用于脉冲驱动段电极的段驱动单元，用于 使得栅极驱动单元的输出的占空比可以变化，用于使段驱动单元的输出的占空比可变的第二控制单元，以及用于选择第一控制单元和/或第二控制单元的选择单元 。
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公开(公告)号：US07221198B2
公开(公告)日：2007-05-22
申请号：US10943141
申请日：2004-09-17
CPC分类号： G06F1/04
摘要： An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.
摘要翻译： 接口电路，响应于控制信号从一个电平变化到另一个电平，输出时钟信号和数据到数据寄存器，该数据寄存器与时钟信号同步地读取数据，以输出时钟信号和数据。 接口电路包括时钟输出电路，当控制信号从一个电平变化到另一个电平时，该时钟输出电路响应于时钟信号的电平，将与数据位数相同的时钟信号的时钟输出到 数据寄存器。
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