公开(公告)号：US20150170972A1

公开(公告)日：2015-06-18

申请号：US14563062

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract translation: 在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源极/漏极区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：US20160190156A1

公开(公告)日：2016-06-30

申请号：US15066297

申请日：2016-03-10

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

公开(公告)号：US20160190016A1

公开(公告)日：2016-06-30

申请号：US15059732

申请日：2016-03-03

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

公开(公告)号：US20160020214A1

公开(公告)日：2016-01-21

申请号：US14867676

申请日：2015-09-28

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD

IPC: H01L27/11 ,  H01L21/311 ,  H01L21/027 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L27/1104 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/0207 ,  H01L27/1108

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

公开(公告)号：US20140035160A1

公开(公告)日：2014-02-06

申请号：US14051078

申请日：2013-10-10

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract translation: 可以通过在第一多个平行路径轨道中形成第一互连图案并且在第二多个平行路径轨道中形成第二互连图案来形成集成电路，其中第二多个路线轨道与第一多个平行路线轨道交替 的路线。 第一互连图案包括第一引线图案，并且第二互连图案包括第二引线图案，使得包含第一引线图案的路径轨道紧邻包含第二引线图案的路径轨迹。 金属互连线形成在第一互连图案和第二互连图案中。 拉伸交叉连接形成在仅连接第一引线和第二引线的垂直连接电平，例如通孔或接触电平。 拉伸交叉连接与其他垂直互连元件同时形成。

公开(公告)号：US20130074028A1

公开(公告)日：2013-03-21

申请号：US13622937

申请日：2012-09-19

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.

Abstract translation: 一种使用DPT兼容的兼容设计规则集和颜色覆盖生成具有DPT兼容互连图案的集成电路的方法。 一种使用减少的DPT兼容设计规则集并使用颜色封面来操作计算机以产生具有DPT兼容互连图案的集成电路的方法。 减少的DPT兼容设计规则集。

公开(公告)号：US20180047728A1

公开(公告)日：2018-02-15

申请号：US15723373

申请日：2017-10-03

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

公开(公告)号：US20170178966A1

公开(公告)日：2017-06-22

申请号：US15447873

申请日：2017-03-02

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L27/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/823475 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

公开(公告)号：US20130244144A1

公开(公告)日：2013-09-19

申请号：US13887651

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Walter BLATCHFORD ,  Yong Seok CHOI ,  Thomas J. ATON

IPC: G03F1/38

CPC classification number: G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract translation: 形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。 相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。 相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。 相邻虚拟特征和最近的门级特征之间的间隔（i）维持栅极间距，或（ii）提供> = 2倍栅极间距的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

公开(公告)号：US20170047329A1

公开(公告)日：2017-02-16

申请号：US15336248

申请日：2016-10-27

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/535

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract translation: 在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源极/漏极区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。