公开(公告)号：US20160005627A1

公开(公告)日：2016-01-07

申请号：US14854140

申请日：2015-09-15

申请人： Texas Instruments Incorporated

发明人： Juan A HERBSOMMER ,  Osvaldo J LOPEZ ,  Jonathan A NOQUIL

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/4825 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32104 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/00

摘要： A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

摘要翻译： 制造功率场效应晶体管封装。 提供了包括平板和与板间隔开的共平面扁平带的引线框架。 板具有第一厚度，并且带具有小于第一厚度的第二厚度。 提供具有第三厚度的场效应晶体管芯片。 产生一个芯片侧的第一和第二接触焊盘和相对芯片侧的第三接触焊盘。 第一个垫子连接到板上，第二个垫子连接到条带上。 端子同时连接到板和条，使得端子与第三接触垫共面。 板和条之间的厚度差以及芯片和端子之间的间隔填充有具有与板共面的表面和与第三焊盘和端子共面的相对表面的封装化合物。 芯片，引线框架和端子集成到具有等于第一和第三厚度之和的厚度的封装中。