公开(公告)号：US12074096B2

公开(公告)日：2024-08-27

申请号：US16793887

申请日：2020-02-18

申请人： Texas Instruments Incorporated

发明人： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Pavone

IPC分类号： H01L23/495 ,  H01L21/683 ,  H01L23/00 ,  H01L23/36 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532

CPC分类号： H01L23/49517 ,  H01L23/49 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/013 ,  H01L2924/00014

摘要： A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US20240222218A1

公开(公告)日：2024-07-04

申请号：US18604957

申请日：2024-03-14

申请人： Taiwan Semiconductor Manufacturing Co, Ltd.

发明人： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC分类号： H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

摘要： A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US11961779B2

公开(公告)日：2024-04-16

申请号：US17331945

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC分类号： H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/291 ,  H01L2924/014

摘要： A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US11804460B2

公开(公告)日：2023-10-31

申请号：US17676602

申请日：2022-02-21

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Jiro Yota ,  Dogan Gunes

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/10

CPC分类号： H01L24/11 ,  H01L23/10 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/0509 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05078 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05558 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29082 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2924/12 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/35121 ,  H01L2224/05558 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05005 ,  H01L2924/00012 ,  H01L2224/05018 ,  H01L2924/00012 ,  H01L2224/05098 ,  H01L2924/06 ,  H01L2224/02125 ,  H01L2924/00012 ,  H01L2224/0215 ,  H01L2924/06 ,  H01L2224/05012 ,  H01L2924/00012 ,  H01L2224/05093 ,  H01L2924/00012 ,  H01L2224/0509 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/83

摘要： Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

公开(公告)号：US11721792B2

公开(公告)日：2023-08-08

申请号：US17157977

申请日：2021-01-25

申请人： eLux Inc.

发明人： Kenji Alexander Sasaki ,  Paul J. Schuele ,  Mark Albert Crowder

IPC分类号： H01L33/00 ,  H01L33/48 ,  H01L33/20 ,  H01L23/00 ,  H01L25/075 ,  H01L25/00 ,  H01L33/62

CPC分类号： H01L33/483 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0753 ,  H01L25/50 ,  H01L33/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/83143 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83488 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/95001 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95136 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2924/10155 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/83815 ,  H01L2924/00014 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2224/83424 ,  H01L2924/00014 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2224/83488 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0105 ,  H01L2224/97 ,  H01L2224/83

摘要： Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.

公开(公告)号：US11711913B2

公开(公告)日：2023-07-25

申请号：US17344942

申请日：2021-06-10

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Weihua Cheng ,  Jun Liu

IPC分类号： H10B10/00 ,  H01L21/76 ,  H01L23/00 ,  G11C14/00 ,  G11C16/04 ,  H01L21/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06 ,  H01L29/04 ,  H01L29/16 ,  H10B12/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H10B10/12 ,  G11C14/0018 ,  G11C16/0483 ,  H01L21/50 ,  H01L21/76 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/04 ,  H01L29/16 ,  H10B12/02 ,  H10B12/033 ,  H10B12/05 ,  H10B12/31 ,  H10B12/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/08145 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/73215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896

摘要： First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US11658154B2

公开(公告)日：2023-05-23

申请号：US16909522

申请日：2020-06-23

申请人： Micron Technology, Inc.

发明人： Seng Kim Ye ,  Hong Wan Ng

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G06F13/16 ,  H01L23/31 ,  H01L21/66 ,  H01L25/03

CPC分类号： H01L25/0657 ,  G06F13/1668 ,  G06F13/1694 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/04 ,  H01L24/16 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L22/14 ,  H01L24/13 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L2224/04042 ,  H01L2224/1319 ,  H01L2224/13083 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2939 ,  H01L2224/29294 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81855 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83874 ,  H01L2224/92227 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/29294 ,  H01L2924/00014 ,  H01L2224/2939 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2224/83874 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/1319 ,  H01L2924/00014 ,  H01L2224/81856 ,  H01L2924/00014 ,  H01L2224/81855 ,  H01L2924/00014 ,  H01L2224/92227 ,  H01L2224/83 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

摘要： Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.

公开(公告)号：US11658150B2

公开(公告)日：2023-05-23

申请号：US17379394

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Feng Yeh ,  Chen-Hua Yu ,  Ming-Fa Chen

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/96 ,  H01L25/50 ,  H01L21/568 ,  H01L23/315 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/291 ,  H01L2224/29076 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/92124 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2224/80001 ,  H01L2224/29186 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/00014

摘要： An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

公开(公告)号：US20190237395A1

公开(公告)日：2019-08-01

申请号：US16378171

申请日：2019-04-08

申请人： Texas Instruments Incorporated

发明人： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC分类号： H01L23/495 ,  H01L25/16 ,  H01L21/48

CPC分类号： H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

摘要： A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20190198376A1

公开(公告)日：2019-06-27

申请号：US16293201

申请日：2019-03-05

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC分类号： H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.