公开(公告)号：US20200319296A1

公开(公告)日：2020-10-08

申请号：US16376515

申请日：2019-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik RAMASUBRAMANIAN

IPC: G01S7/35

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

公开(公告)号：US20250035744A1

公开(公告)日：2025-01-30

申请号：US18476965

申请日：2023-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Sandeep RAO ,  Karthik RAMASUBRAMANIAN

IPC: G01S7/40 ,  G01S7/35 ,  G01S13/931

Abstract: In some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target. The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency. The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

公开(公告)号：US20240288563A1

公开(公告)日：2024-08-29

申请号：US18654683

申请日：2024-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN ,  Shailesh JOSHI ,  Kameswaran VENGATTARAMANE ,  Indu PRATHAPAN

IPC: G01S13/04 ,  G01S7/35 ,  G06F16/22 ,  G06F16/901 ,  G06F17/14

CPC classification number: G01S13/04 ,  G01S7/35 ,  G06F16/2264 ,  G06F16/9017 ,  G06F17/142

Abstract: Systems and instruction carrying non-transitory processor-readable mediums are provided to facilitate access of radar data that may be scattered or non-uniformly located within a region of memory for further processing of such radar data. An example system includes counters that increment on different dimensions of the memory region, a lookup table, multipliers, an adder, and a wraparound mechanism to access different sets of non-contiguously stored radar data from a region of memory. The wraparound mechanism performs a wraparound operation when a combined address, generated by the adder based on addresses obtained by the multipliers, is greater than a last valid address in the region. The wraparound operation generates a new combined address that is used to fetch data from the memory. A transform operation is then performed on the fetched data.

公开(公告)号：US20220155368A1

公开(公告)日：2022-05-19

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata RAMALINGAM ,  Karthik SUBBURAJ ,  Pankaj GUPTA ,  Anil Varghese MANI ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G01R31/317 ,  G01R29/26 ,  G11C19/28 ,  G01S7/40

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20240345805A1

公开(公告)日：2024-10-17

申请号：US18753107

申请日：2024-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.

公开(公告)号：US20220366004A1

公开(公告)日：2022-11-17

申请号：US17357919

申请日：2021-06-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh JOSHI ,  Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN

IPC: G06F17/14

Abstract: A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

公开(公告)号：US20130116921A1

公开(公告)日：2013-05-09

申请号：US13668381

申请日：2012-11-05

Applicant: Texas Instruments Incorporated

Inventor： Sandeep KASARGOD ,  Sandeep RAO ,  Karthik RAMASUBRAMANIAN ,  Tarkesh PANDE ,  Sriram MURALI

IPC: G01S19/45 ,  G01S19/42 ,  G01C21/12

CPC classification number: G01C21/12 ,  G01C21/165 ,  G01S19/42 ,  G01S19/45

Abstract: A vehicle navigation system includes a GNSS position engine (GPE) that uses GNSS satellite measurements to compute a first position and velocity of a vehicle and a first quality metric associated with the position and velocity. The system also includes a dead reckoning engine (DRE) that operates parallel with the GPE that computes a second position and velocity and a second quality metric associated with the dead reckoning. The GPE is configured to use the second position and velocity to detect a set of outliers in an incoming GNSS measurement; use the second position and velocity as an initial estimate of its position and velocity for a particular time instant, which is then refined by GNSS measurements received at that particular time instant; and to replace the first position and velocity with the second position and velocity.

Abstract translation: 车辆导航系统包括使用GNSS卫星测量来计算车辆的第一位置和速度以及与位置和速度相关联的第一质量度量的GNSS位置引擎（GPE）。 该系统还包括与计算第二位置和速度的GPE并行运行的航位推算引擎（DRE），以及与推算相关联的第二质量度量。 GPE被配置为使用第二位置和速度来检测进入GNSS测量中的一组异常值; 使用第二位置和速度作为其在特定时间瞬间的位置和速度的初始估计，然后通过在该特定时刻接收的GNSS测量来改进; 并用第二位置和速度来替换第一位置和速度。

公开(公告)号：US20220156044A1

公开(公告)日：2022-05-19

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F9/355 ,  G06F17/14 ,  G06F16/901

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US20220120884A1

公开(公告)日：2022-04-21

申请号：US17351654

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN ,  Shailesh JOSHI ,  Kameswaran VENGATTARAMANE ,  Indu PRATHAPAN

IPC: G01S13/04 ,  G01S7/35 ,  G06F17/14 ,  G06F16/22 ,  G06F16/901

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

公开(公告)号：US20200309939A1

公开(公告)日：2020-10-01

申请号：US16363719

申请日：2019-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Sandeep RAO ,  Sriram MURALI ,  Karthik RAMASUBRAMANIAN

IPC: G01S13/58 ,  G01S7/35

Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.