公开(公告)号：US08877622B2

公开(公告)日：2014-11-04

申请号：US13811792

申请日：2011-07-22

申请人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

发明人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/115 ,  H01L21/768

CPC分类号： H01L21/823468 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11521

摘要： A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

摘要翻译： 一种用于在基板表面上制造集成电路的方法，所述方法包括：在所述基板的表面上产生包括有源区和绝缘区的第一层; 在所述第一层的表面上产生栅极区域，所述栅极区域各自被绝缘间隔物包围; 产生源极/漏极; 在所述绝缘间隔物之间​​产生电介质层，所述电介质层具有与所述栅极区的上表面的上表面水平; 部分地蚀刻每个栅极区，以便降低每个栅极区的第一部分的上表面; 以及在栅极区域的第一部分上沉积绝缘介电层。

公开(公告)号：US20130252412A1

公开(公告)日：2013-09-26

申请号：US13811792

申请日：2011-07-22

申请人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

发明人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

IPC分类号： H01L21/8234

CPC分类号： H01L21/823468 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11521

摘要： A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

摘要翻译： 一种用于在基板表面上制造集成电路的方法，所述方法包括：在所述基板的表面上产生包括有源区和绝缘区的第一层; 在所述第一层的表面上产生栅极区域，所述栅极区域各自被绝缘间隔物包围; 产生源极/漏极; 在所述绝缘间隔物之间​​产生电介质层，所述电介质层具有与所述栅极区的上表面的上表面水平; 部分地蚀刻每个栅极区，以便降低每个栅极区的第一部分的上表面; 以及在栅极区域的第一部分上沉积绝缘介电层。

公开(公告)号：US08530292B2

公开(公告)日：2013-09-10

申请号：US13229081

申请日：2011-09-09

申请人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

发明人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

IPC分类号： H01L21/20

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76283 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7846

摘要： A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

摘要翻译： 一种制造应变通道MOS晶体管的方法，包括以下步骤：在半导体衬底的表面形成包括源极和漏极区域的MOS晶体管和绝缘牺牲栅极，其部分地延伸超过围绕晶体管的绝缘区域; 形成具有其上表面水平的电介质材料层与牺牲栅极的上表面; 去除牺牲门; 蚀刻暴露的绝缘区域的至少上部以在其中形成沟槽; 用能够向基材施加应变的材料填充沟槽; 并且在由牺牲栅极留下的空间中形成绝缘的MOS晶体管栅极。

公开(公告)号：US07361592B2

公开(公告)日：2008-04-22

申请号：US11444423

申请日：2006-06-01

申请人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

发明人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

IPC分类号： H01L21/44

CPC分类号： H01L21/76251

摘要： The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.

摘要翻译： 该方法依次包括在衬底上生产包括由锗制成的至少一个第一层和最初具有10％至5​​0％的锗浓度的硅化合物的层叠层。 第一层布置在锗浓度介于0％和10％之间的第二层之间。 然后通过在所述堆叠中的蚀刻来描绘对应于锗基元件并且具有在10nm和500nm之间的至少第一横向尺寸的第一区域。 然后，至少进行第一区域的侧向热氧化，使得在第一区域的表面上形成二氧化硅层，并且在第一层中形成构成锗基元素的浓缩锗的中心区域。

公开(公告)号：US20060276052A1

公开(公告)日：2006-12-07

申请号：US11444423

申请日：2006-06-01

申请人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

发明人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

IPC分类号： H01L21/31

CPC分类号： H01L21/76251

摘要： The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.

摘要翻译： 该方法依次包括在衬底上生产包括由锗制成的至少一个第一层和最初具有10％至5​​0％的锗浓度的硅化合物的层叠层。 第一层布置在锗浓度介于0％和10％之间的第二层之间。 然后通过在所述堆叠中的蚀刻来描绘对应于锗基元件并且具有在10nm和500nm之间的至少第一横向尺寸的第一区域。 然后，至少进行第一区域的侧向热氧化，使得在第一区域的表面上形成二氧化硅层，并且在第一层中形成构成锗基元素的浓缩锗的中心区域。

公开(公告)号：US08598038B2

公开(公告)日：2013-12-03

申请号：US13187784

申请日：2011-07-21

申请人： Yves Morand ,  Thierry Poiroux

发明人： Yves Morand ,  Thierry Poiroux

IPC分类号： H01L21/311

CPC分类号： H01L21/0334 ,  H01L21/0337

摘要： A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

摘要翻译： 用于在衬底上产生两个交错图案的工艺使用光刻和蚀刻在衬底上产生由凹陷区域分开的第一材料突出区域的第一图案。 在第一图案上的第二材料的非共形沉积在第一图案的凹陷区域中形成空腔。 这些空腔被打开并填充有第三种材料。 然后去除第二材料，剩余的第三材料形成第三材料突出区域的第二图案，其中第二图案与第一图案交错。

公开(公告)号：US20120153394A1

公开(公告)日：2012-06-21

申请号：US13229081

申请日：2011-09-09

申请人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

发明人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76283 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7846

摘要： A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

摘要翻译： 一种制造应变通道MOS晶体管的方法，包括以下步骤：在半导体衬底的表面形成包括源极和漏极区域的MOS晶体管和绝缘牺牲栅极，其部分地延伸超过围绕晶体管的绝缘区域; 形成具有其上表面水平的电介质材料层与牺牲栅极的上表面; 去除牺牲门; 蚀刻暴露的绝缘区域的至少上部以在其中形成沟槽; 用能够向基材施加应变的材料填充沟槽; 并且在由牺牲栅极留下的空间中形成绝缘的MOS晶体管栅极。

公开(公告)号：US07829916B2

公开(公告)日：2010-11-09

申请号：US11920835

申请日：2006-05-23

申请人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

发明人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

IPC分类号： H01L29/66 ,  H01L21/44

CPC分类号： H01L29/785 ,  H01L29/42392

摘要： Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

摘要翻译： 源电极和漏电极各自由锗和硅化合物制成的第一和第二层的交替形成。 第一层的锗浓度介于0％和10％之间，第二层的锗浓度在10％至5​​0％之间。 至少一个通道分别连接源电极和漏电极的两个第二层。 该方法包括以层叠的方式蚀刻通过窄带连接的源区和漏区。 然后执行所述堆叠的表面热氧化，以便使锗浓度在10％至5​​0％之间的锗和硅化合物的硅氧化并使锗Ge冷凝。 去除窄区域的氧化硅，并且在狭窄区域的浓缩锗上沉积栅极电介质和栅极。

公开(公告)号：US20120021606A1

公开(公告)日：2012-01-26

申请号：US13187784

申请日：2011-07-21

申请人： Yves Morand ,  Thierry Poiroux

发明人： Yves Morand ,  Thierry Poiroux

IPC分类号： H01L21/311

CPC分类号： H01L21/0334 ,  H01L21/0337

摘要： A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

摘要翻译： 用于在衬底上产生两个交错图案的工艺使用光刻和蚀刻在衬底上产生由凹陷区域分开的第一材料突出区域的第一图案。 在第一图案上的第二材料的非共形沉积在第一图案的凹陷区域中形成空腔。 这些空腔被打开并填充有第三种材料。 然后去除第二材料，剩余的第三材料形成第三材料突出区域的第二图案，其中第二图案与第一图案交错。

公开(公告)号：US20090127584A1

公开(公告)日：2009-05-21

申请号：US11920835

申请日：2006-05-23

申请人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

发明人： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

IPC分类号： H01L29/80 ,  H01L21/26

CPC分类号： H01L29/785 ,  H01L29/42392

摘要： Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

摘要翻译： 源电极和漏电极各自由锗和硅化合物制成的第一和第二层的交替形成。 第一层的锗浓度介于0％至10％之间，第二层的锗浓度介于10％至5​​0％之间。 至少一个通道分别连接源电极和漏电极的两个第二层。 该方法包括以层叠的方式蚀刻通过窄带连接的源区和漏区。 然后执行所述堆叠的表面热氧化，以便使锗浓度在10％至5​​0％之间的锗和硅化合物的硅氧化并使锗Ge冷凝。 去除窄区域的氧化硅，并且在狭窄区域的浓缩锗上沉积栅极电介质和栅极。