公开(公告)号：US20100237431A1

公开(公告)日：2010-09-23

申请号：US12791290

申请日：2010-06-01

Applicant: Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

Inventor： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract translation: 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

公开(公告)号：US20090001484A1

公开(公告)日：2009-01-01

申请号：US12027583

申请日：2008-02-07

Applicant: Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

Inventor： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC: H01L29/00 ,  H01L21/8236

CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract translation: 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

公开(公告)号：US08183605B2

公开(公告)日：2012-05-22

申请号：US12791290

申请日：2010-06-01

Applicant: Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

Inventor： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC: H01L29/80 ,  H01L27/01 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425

CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract translation: 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

公开(公告)号：US07754556B2

公开(公告)日：2010-07-13

申请号：US12027583

申请日：2008-02-07

Applicant: Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

Inventor： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/425 ,  H01L29/80 ,  H01L27/10

CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract translation: 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

公开(公告)号：US20120223309A1

公开(公告)日：2012-09-06

申请号：US13474934

申请日：2012-05-18

Applicant: Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L23/58

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20080081403A1

公开(公告)日：2008-04-03

申请号：US11740072

申请日：2007-04-25

Applicant: Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

Inventor： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

IPC: H01L21/337

CPC classification number: H01L29/045 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.

Abstract translation: 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。

公开(公告)号：US08227266B2

公开(公告)日：2012-07-24

申请号：US12716472

申请日：2010-03-03

Applicant: Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20090166618A1

公开(公告)日：2009-07-02

申请号：US12132014

申请日：2008-06-03

Applicant: Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L23/58 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20100155727A1

公开(公告)日：2010-06-24

申请号：US12716472

申请日：2010-03-03

Applicant: ANTHONY MOWRY ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： ANTHONY MOWRY ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20080001178A1

公开(公告)日：2008-01-03

申请号：US11674713

申请日：2007-02-14

Applicant: Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

Inventor： Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract translation: 通过在栅电极中形成应力半导体材料，可以在沟道区域中诱发双轴拉伸应变，从而显着提高载流子迁移率。 该概念可以有利地与额外的应变诱发源（例如在漏极和源极区域中的嵌入式应变半导体材料）结合，从而提供增强晶体管性能的潜力，而不会造成工艺复杂性。