HID buck and full-bridge ballast control IC
    2.
    发明授权
    HID buck and full-bridge ballast control IC 有权
    HID降压和全桥镇流器控制IC

    公开(公告)号:US07525256B2

    公开(公告)日:2009-04-28

    申请号:US11263751

    申请日:2005-10-28

    IPC分类号: H05B37/02

    摘要: An integrated circuit controls a power converter that includes single stage buck-boost converter and a switching full bridge that may be used to drive an HID lamp. The single stage buck-boost converter reduces the complexity and parts count of the power converter, or electronic ballast, while permitting PFC and DC bus voltage regulation under control of the integrated circuit to maintain constant power on the HID lamp. The integrated circuit simplifies the design of power converters and electronic ballasts in particular, while reducing part count, complexity and cost in conjunction with the single stage buck-boost converter and the full bridge switching circuit.

    摘要翻译: 集成电路控制包括单级降压 - 升压转换器和可用于驱动HID灯的开关全桥的功率转换器。 单级降压 - 升压转换器降低了功率转换器或电子镇流器的复杂性和部件数量,同时允许集成电路控制下的PFC和DC总线电压调节,以保持HID灯上的恒定功率。 集成电路特别简化了功率转换器和电子镇流器的设计,同时降低了单级降压 - 升压转换器和全桥开关电路的部件数量,复杂性和成本。

    Power factor correction integrated circuit with critical conduction mode
    3.
    发明授权
    Power factor correction integrated circuit with critical conduction mode 有权
    具有临界导通模式的功率因数校正集成电路

    公开(公告)号:US08174855B2

    公开(公告)日:2012-05-08

    申请号:US11548928

    申请日:2006-10-12

    IPC分类号: H02M7/217

    摘要: A power factor correction integrated circuit housed in an integrated circuit package for controlling a boost converter circuit having an input inductor coupled in series with a boost rectifier between a rectified AC line input voltage and a DC bus voltage, on a DC bus, the rectified AC line input voltage provided by a rectifier coupled to an AC line input voltage to be power factor corrected. The integrated circuit including a first input circuit sensing the DC bus voltage; a second input circuit sensing current through the inductor and determining when the current through the inductor discharges to substantially zero current, a power switch coupled between a common connection of the inductor and boost rectifier and a return line of the DC bus for allowing the inductor to be charged by current from the rectified AC line input voltage when the power switch is turned on; and a control circuit having inputs coupled to outputs from the first and second input circuits to control the On-Time of the power switch to regulate the DC bus voltage to a desired voltage level and to achieve power factor correction of the AC line input voltage.

    摘要翻译: 一种功率因数校正集成电路,其容纳在集成电路封装中,用于控制升压转换器电路,该升压转换器电路具有与DC总线上的整流的AC线路输入电压和DC总线电压之间的升压整流器串联的输入电感器,整流的AC 由耦合到AC线输入电压的整流器提供的线路输入电压被功率因数校正。 所述集成电路包括感测所述直流母线电压的第一输入电路; 第二输入电路感测通过电感器的电流,并确定何时通过电感器的电流放电至基本为零的电流;耦合在电感器和升压整流器的公共连接之间的电源开关和DC总线的返回线, 当电源开关打开时,由整流的交流线路输入电压由电流充电; 以及控制电路,其具有耦合到来自第一和第二输入电路的输出的输入,以控制电源开关的导通时间,以将DC总线电压调节到期望的电压电平并且实现AC线路输入电压的功率因数校正。

    Ballast control circuit
    4.
    发明授权
    Ballast control circuit 有权
    镇流器控制电路

    公开(公告)号:US07436127B2

    公开(公告)日:2008-10-14

    申请号:US11555922

    申请日:2006-11-02

    IPC分类号: H05B37/02

    摘要: A ballast control circuit having a bridge driver for driving a transistor bridge of a ballast circuit coupled to a resonant ballast output stage including a lamp, the ballast control circuit comprising a circuit for setting a minimum oscillation frequency and a voltage controlled oscillation circuit having a first input, wherein as a voltage at the first input increases, modes of the circuit change from a preheat mode where the frequency of oscillation moves from a first frequency to a lower preheat frequency and continues at a substantially constant preheat frequency for a set duration of preheat time, to an ignition mode where the frequency moves lower towards a resonance frequency of the ballast output stage until the lamp ignites, and to a run mode where the frequency stops decreasing and stays at the minimum set frequency.

    摘要翻译: 一种镇流器控制电路,其具有用于驱动耦合到包括灯的谐振镇流器输出级的镇流器电路的晶体管桥的桥接驱动器,所述镇流器控制电路包括用于设置最小振荡频率的电路和具有第一 输入,其中当所述第一输入处的电压增加时,所述电路的模式从所述振荡频率从第一频率移动到较低预热频率的预热模式改变,并以基本上恒定的预热频率继续预定的持续时间 时间到点火模式,其中频率向镇流器输出级的谐振频率向下移动直到灯点亮,并且到频率停止下降并保持在最小设定频率的运行模式。

    Adaptive CFL control circuit
    5.
    发明授权
    Adaptive CFL control circuit 有权
    自适应CFL控制电路

    公开(公告)号:US06891339B2

    公开(公告)日:2005-05-10

    申请号:US10664676

    申请日:2003-09-18

    CPC分类号: H05B41/2828 H05B41/2981

    摘要: An electronic ballast provides fault detection and safety features for overcurrent protection and hard switching at a half bridge. A voltage controlled oscillator supplies a switching frequency that is modifiable based on operationalfeedback parameters. A feedback circuit senses load current and output voltage to determiner fault conditions and to provide control information for adaptively adjusting the frequency of the voltage controlled oscillator. By appropriately controlling the voltage controlled oscillator output, the electronic ballast maintains a zero volt switching with minimum current switching to achieve an efficient and robust electronic ballast control. The entire control is integrated on a single integrated circuit.

    摘要翻译: 电子镇流器为半桥过流保护和硬开关提供故障检测和安全功能。 压控振荡器提供基于操作反馈参数可修改的开关频率。 反馈电路感测负载电流和输出电压到确定器故障条件,并提供用于自适应调节压控振荡器频率的控制信息。 通过适当地控制压控振荡器输出,电子镇流器通过最小电流切换保持零伏开关,以实现有效和鲁棒的电子镇流器控制。 整个控制集成在单个集成电路上。

    Automotive HID headlamp ballast control IC
    6.
    发明授权
    Automotive HID headlamp ballast control IC 有权
    汽车HID前照灯镇流器控制IC

    公开(公告)号:US08093834B2

    公开(公告)日:2012-01-10

    申请号:US12026044

    申请日:2008-02-05

    IPC分类号: H05B37/02

    摘要: A ballast control integrated circuit for a ballast driving a high intensity discharge (HID) lamp. The control integrated circuit has a first circuit for controlling a DC to DC converter receiving a first DC voltage and providing an increased DC voltage. The first circuit includes a driver for providing a pulsed signal to drive a first switch coupled to a flyback transformer of the DC to DC converter. A second circuit controls a DC to AC converter, the second circuit controlling a switching circuit receiving the increased DC voltage and driving the HID lamp with an AC voltage. The second circuit has a driver circuit for driving the switching circuit. The switching circuit is an H-bridge switching circuit coupled to drive the HID lamp.

    摘要翻译: 用于镇流器的镇流器控制集成电路驱动高强度放电(HID)灯。 控制集成电路具有用于控制DC-DC转换器的第一电路,其接收第一DC电压并提供增加的DC电压。 第一电路包括用于提供脉冲信号以驱动耦合到DC-DC转换器的回扫变压器的第一开关的驱动器。 第二电路控制DC到AC转换器,第二电路控制接收升高的直流电压并用AC电压驱动HID灯的开关电路。 第二电路具有用于驱动开关电路的驱动电路。 开关电路是耦合以驱动HID灯的H桥开关电路。

    BALLAST CONTROL CIRCUIT
    7.
    发明申请
    BALLAST CONTROL CIRCUIT 有权
    压力控制电路

    公开(公告)号:US20070096662A1

    公开(公告)日:2007-05-03

    申请号:US11555922

    申请日:2006-11-02

    IPC分类号: H05B41/36

    摘要: A ballast control circuit having a bridge driver for driving a transistor bridge of a ballast circuit coupled to a resonant ballast output stage including a lamp, the ballast control circuit comprising a circuit for setting a minimum oscillation frequency and a voltage controlled oscillation circuit having a first input, wherein as a voltage at the first input increases, modes of the circuit change from a preheat mode where the frequency of oscillation moves from a first frequency to a lower preheat frequency and continues at a substantially constant preheat frequency for a set duration of preheat time, to an ignition mode where the frequency moves lower towards a resonance frequency of the ballast output stage until the lamp ignites, and to a run mode where the frequency stops decreasing and stays at the minimum set frequency.

    摘要翻译: 一种镇流器控制电路,其具有用于驱动耦合到包括灯的谐振镇流器输出级的镇流器电路的晶体管桥的桥接驱动器,所述镇流器控制电路包括用于设置最小振荡频率的电路和具有第一 输入,其中当所述第一输入处的电压增加时,所述电路的模式从所述振荡频率从第一频率移动到较低预热频率的预热模式改变,并以基本上恒定的预热频率继续预定的持续时间 时间到点火模式,其中频率向镇流器输出级的谐振频率向下移动直到灯点亮,并且到频率停止下降并保持在最小设定频率的运行模式。

    Half bridge adaptive dead time circuit and method
    8.
    发明申请
    Half bridge adaptive dead time circuit and method 有权
    半桥自适应死区电路及方法

    公开(公告)号:US20050184714A1

    公开(公告)日:2005-08-25

    申请号:US11062010

    申请日:2005-02-18

    IPC分类号: G05F1/40 H02M1/38

    摘要: A high voltage offset detection circuit registers the voltage at the midpoint of a switching half-bridge and may determine when the midpoint voltage reaches a given value to avoid hard-switching in the half-bridge switches. The midpoint voltage of the switching half-bridge is applied through a buffer to a MOSFET that is current limited to produce a voltage that reflects the voltage of the midpoint of the switching half-bridge. The voltage produced by the MOSFET may be supplied to a comparator with a threshold input to obtain a signal that indicates when the switches of the switching half-bridge may be turned on to avoid hard-switching. An adaptive dead-time circuit and method may comprise the above sensing circuit, a first circuit for generating a first signal indicative of a high to low transition of the midpoint voltage; and an output circuit for generating an adaptive dead-time output signal based thereon. A second circuit may generate a second signal indicative of a low to high transition of the voltage; wherein the output circuit generates the adaptive dead-time output signal based on both the first and second signals. The second circuit preferably generates the second signal by reproducing the first signal. The first circuit may generate the first signal by charging a capacitor in response to pulses, and the second circuit may generate the second signal by charging a second capacitor corresponding to said first capacitor, and the adaptive dead-time output signal may be responsive to the charges on the first and second capacitors.

    摘要翻译: 高电压失调检测电路在开关半桥的中点登记电压,并且可以确定中点电压何时达到给定值以避免半桥开关中的硬切换。 开关半桥的中点电压通过缓冲器施加到电流限制的MOSFET,以产生反映开关半桥中点电压的电压。 由MOSFET产生的电压可以提供给具有阈值输入的比较器,以获得指示开关半桥的开关何时导通以避免硬切换的信号。 自适应死区时间电路和方法可以包括上述感测电路,用于产生指示中点电压的高到低转换的第一信号的第一电路; 以及用于基于此产生自适应死区时间输出信号的输出电路。 第二电路可以产生指示电压的低到高转换的第二信号; 其中所述输出电路基于所述第一和第二信号两者产生所述自适应死区时间输出信号。 第二电路优选地通过再现第一信号来产生第二信号。 第一电路可以通过响应于脉冲对电容器充电来产生第一信号,并且第二电路可以通过对与所述第一电容器相对应的第二电容器进行充电来产生第二信号,并且自适应死区时间输出信号可以响应于 在第一和第二电容器上充电。

    Bootstrap diode emulator with dynamic back-gate biasing
    9.
    发明申请
    Bootstrap diode emulator with dynamic back-gate biasing 有权
    具有动态背栅偏置的自举二极管仿真器

    公开(公告)号:US20050102128A1

    公开(公告)日:2005-05-12

    申请号:US10712893

    申请日:2003-11-12

    申请人: Dana Wilhelm

    发明人: Dana Wilhelm

    摘要: A bootstrap diode emulator circuit for use in a half-bridge switching circuit employing transistors connected to one another in a totem pole configuration, a driver circuit for driving the transistors, and a bootstrap capacitor for providing power to the high-side driver circuit. The bootstrap diode emulator circuit includes an LDMOS transistor having a gate, a back-gate, a source and a drain, the drain of the LDMOS transistor being coupled to the high-side supply node, the source of the LDMOS transistor being coupled to the low-side supply node; a gate control circuit electrically coupled to the gate of the LDMOS transistor, and a dynamic back-gate biasing circuit electrically coupled to the back-gate of the LDMOS transistor. The dynamic back-gate biasing circuit is operable to dynamically bias the back-gate of the LDMOS transistor when the LDMOS is turned on by applying a voltage to the back-gate of the LDMOS transistor that is close to but slightly lower than a voltage of the drain of the LDMOS transistor.

    摘要翻译: 一种用于半桥开关电路的自举二极管仿真器电路,所述半桥开关电路采用以图腾柱结构彼此连接的晶体管,用于驱动晶体管的驱动电路,以及用于向高侧驱动电路提供电力的自举电容器。 自举二极管仿真器电路包括具有栅极,后栅极,源极和漏极的LDMOS晶体管,LDMOS晶体管的漏极耦合到高侧供电节点,LDMOS晶体管的源极耦合到 低侧供应节点; 电耦合到LDMOS晶体管的栅极的栅极控制电路和电耦合到LDMOS晶体管的背栅极的动态背栅极偏置电路。 动态背栅极偏置电路可操作以通过向LDMOS晶体管的背栅极施加电压而使LDMOS晶体管的背栅极接通但略低于LDMOS晶体管的电压时,动态地偏置LDMOS晶体管的背栅极 LDMOS晶体管的漏极。

    MOSFET driver with fault reporting outputs
    10.
    发明授权
    MOSFET driver with fault reporting outputs 失效
    具有故障报告输出的MOSFET驱动器

    公开(公告)号:US5543994A

    公开(公告)日:1996-08-06

    申请号:US394702

    申请日:1995-02-27

    摘要: The fault latch and filter circuit used in a MOSgated driver for a high side power MOSgated device to turn off the MOSgated device high side output in response to a given fault condition is located in the high side of the circuit and in a floating well of a semiconductor chip containing the driver circuit. The fault latch and filter are connected to the output driver circuit through a gate which also receives the high side filter and latch which are operated by the input control logic circuits through a level-shift up circuit. The fault latch circuit has an output which is level-shifted down by a single PMOS device to a fault reporting latch circuit on the low side of the device.

    摘要翻译: 在用于高边功率MOS器件的MOS驱动器中使用的故障锁存器和滤波器电路,以响应于给定的故障条件来关断MOS器件的高侧输出,位于电路的高侧和位于电路的浮动阱中 半导体芯片包含驱动电路。 故障锁存器和滤波器通过栅极连接到输出驱动器电路,栅极还接收由输入控制逻辑电路通过电平转换上升电路操作的高侧滤波器和锁存器。 故障锁存电路具有由单个PMOS器件向下电平的输出到器件低端的故障报告锁存电路。