公开(公告)号：US06992670B2

公开(公告)日：2006-01-31

申请号：US10746787

申请日：2003-12-23

申请人： Thomas L. Thrasher ,  Ronald D. Larson

发明人： Thomas L. Thrasher ,  Ronald D. Larson

IPC分类号： G06T11/20 ,  G06T15/00 ,  G06F17/50

CPC分类号： G06T11/203

摘要： In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

公开(公告)号：US06753861B2

公开(公告)日：2004-06-22

申请号：US09982352

申请日：2001-10-18

申请人： Thomas L Thrasher ,  Ronald D. Larson

发明人： Thomas L Thrasher ,  Ronald D. Larson

IPC分类号： G06T1120

CPC分类号： G06T11/203

摘要： In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

公开(公告)号：US06943804B2

公开(公告)日：2005-09-13

申请号：US10283665

申请日：2002-10-30

申请人： Byron A. Alcorn ,  Ronald D. Larson ,  Larry Jay Thayer

发明人： Byron A. Alcorn ,  Ronald D. Larson ,  Larry Jay Thayer

IPC分类号： G06T15/00 ,  G06T15/04 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/37 ,  G09G5/393

CPC分类号： G09G5/393 ,  G06T15/005 ,  G06T15/04 ,  G09G5/14 ,  G09G5/363

摘要： Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.

摘要翻译： 提供了用于执行BLT（BLock Transfer）的系统和方法。 根据一个实施例，一种方法使用纹理映射子系统通过将纹理映射子系统配置为与要传送的像素块对应的坐标值来执行BLT。 根据另一实施例，一种装置包括用于从对应于帧缓冲器的存储器的源段定义纹理映射的逻辑，用于配置具有对应于显示器上的第一像素块的坐标值的纹理映射子系统的逻辑，逻辑 用于使用纹理映射子系统将由配置的坐标值定义的纹理映射应用于对应于图形显示器上的第二像素块的存储器的目的地段，其中纹理映射的应用影响数据的BLT 第一个像素块到第二个像素块。

公开(公告)号：US5420980A

公开(公告)日：1995-05-30

申请号：US33090

申请日：1993-03-16

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393 ,  G06T15/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US5251296A

公开(公告)日：1993-10-05

申请号：US494997

申请日：1990-03-16

申请人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

发明人： Desi Rhoden ,  Byron A. Alcorn ,  Darel N. Emmot ,  Ronald D. Larson

IPC分类号： G06F12/06 ,  G06T1/60 ,  G06T15/80 ,  G09G5/39 ,  G06F15/20 ,  G06F15/00

CPC分类号： G09G5/39 ,  G06T15/80 ,  G09G2360/122

摘要： Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

公开(公告)号：US07064752B1

公开(公告)日：2006-06-20

申请号：US09172389

申请日：1998-10-14

申请人： Ronald D. Larson

发明人： Ronald D. Larson

IPC分类号： G06T15/00

CPC分类号： G06T15/405

摘要： A multi-function unit for occlusion testing primitives being processed in a graphics system and for updating a Z pyramid data structure used for occlusion testing. The Z pyramid data structure is updated on the fly, i.e., as primitives are being occlusion tested. The apparatus comprises multi-function unit is configured to create the Z pyramid data structure and to perform occlusion testing. The Z pyramid data structure comprises a plurality of levels, each of which comprises a plurality of regions. Each region comprises a plurality of subregions, each of which corresponds to a single Z value. Each region corresponds to a plurality of Z values and has a maximum region Z value, which corresponds to the largest Z value of the region. The multi-function unit compares the minimum Z value of each primitive with the maximum Z value of a region associated with the tested primitive to determine whether or not the tested primitive is fully occluded. Coverage masks are maintained by the multi-function unit for the different levels of the Z pyramid data structure to enable the Z pyramid data structure to be updated on the fly. When certain bits in the coverage masks are set, the multi-function unit causes the Z pyramid data structure to be updated.

摘要翻译： 用于在图形系统中处理遮挡测试原语的多功能单元，以及用于更新用于遮挡测试的Z金字塔数据结构。 Z金字塔数据结构即时更新，即原始图像被遮挡测试。 该装置包括多功能单元，用于创建Z金字塔数据结构并执行遮挡测试。 Z金字塔数据结构包括多个级别，每个级别包括多个区域。 每个区域包括多个子区域，每个子区域对应于单个Z值。 每个区域对应于多个Z值，并且具有对应于该区域的最大Z值的最大区域Z值。 多功能单元将每个基元的最小Z值与与测试图元相关联的区域的最大Z值进行比较，以确定被测图元是否被完全遮挡。 覆盖掩码由多功能单元维护，用于不同级别的Z金字塔数据结构，以使Z金字塔数据结构能够即时更新。 当覆盖掩码中的某些位被设置时，多功能单元使Z金字塔数据结构更新。

公开(公告)号：US06359623B1

公开(公告)日：2002-03-19

申请号：US09190666

申请日：1998-11-12

申请人： Ronald D. Larson

发明人： Ronald D. Larson

IPC分类号： G06F1500

CPC分类号： G06T11/40 ,  G06T15/405

摘要： A method and apparatus for performing scan conversion in a computer graphics display system to determine pixel locations in screen space which correspond to a primitive being scan converted. The apparatus of the present invention comprises logic configured to convert a primitive into pixel locations in screen space. The logic, which is referred to hereinafter as the hierarchical tiler, subdivides the screen space into a plurality of regions, each of which comprises a plurality of pixel locations in screen space. The hierarchical tiler then determines whether a particular one of the regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular region is entirely inside of the primitive, it converts the particular region into pixel locations in screen space. If the hierarchical tiler determines that the particular region is partially inside of the primitive, it further subdivides the particular region into a plurality of sub-regions. The hierarchical tiler then determines whether a particular one of the plurality of sub-regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular sub-region is entirely inside of the primitive, it converts the particular sub-region into pixel locations in screen space. This process of subdividing the screen space into smaller regions continues until either a region is found to be contained within a primitive and is converted into pixels, or until screen space has been subdivided all of the way down to the pixel level.

摘要翻译： 一种用于在计算机图形显示系统中执行扫描转换以确定对应于被扫描转换的原语的屏幕空间中的像素位置的方法和装置。 本发明的装置包括被配置为将原始图像转换成屏幕空间中的像素位置的逻辑。 在下文中称为分级层次机的逻辑将屏幕空间细分为多个区域，每个区域包括屏幕空间中的多个像素位置。 然后，层级层次结构确定区域中的特定区域是否完全在图元之外，完全在图元的内部，或部分地在图元的内部。 如果分级层次结构确定特定区域完全在原始内部，则将特定区域转换为屏幕空间中的像素位置。 如果分级层次结构确定特定区域部分在原语内部，则其进一步将特定区域细分为多个子区域。 然后，分级层级器确定多个子区域中的特定一个子区域是否完全在原始图元之外，完全在图元的内部，或部分地在图元的内部。 如果层次结构确定特定子区域完全位于基元内部，则将特定子区域转换为屏幕空间中的像素位置。 将屏幕空间细分成较小区域的这个过程继续进行，直到发现一个区域被包含在一个图元内并被转换为像素，或者直到屏幕空间已经被全部细分为像素级。

公开(公告)号：US5224210A

公开(公告)日：1993-06-29

申请号：US900535

申请日：1992-06-18

申请人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Darel N. Emmot ,  Ronald D. Larson ,  Byron A. Alcorn ,  Desi Rhoden

IPC分类号： G09G5/14 ,  G09G5/393

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G2360/121

摘要： Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

摘要翻译： 使用图形管线和图形管道旁路总线的图形窗口系统。 公开了用于图形基元的窗口相对渲染的硬件解决方案，块图形基元的移动，大数据块的传送以及消除管道冲洗。 根据本发明提供的硬件实现沿着流水线旁路总线接口，从而消除了图形管线的总开销处理器时间并减少了流水线延迟。 根据本发明提供的方法和装置显示出显着的流水线效率和缩短将图形图元渲染到屏幕系统的时间。

公开(公告)号：US07629979B2

公开(公告)日：2009-12-08

申请号：US10644215

申请日：2003-08-20

申请人： Darel N. Emmot ,  Byron A. Alcorn ,  Ronald D. Larson

发明人： Darel N. Emmot ,  Byron A. Alcorn ,  Ronald D. Larson

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F12/02 ,  G06F13/14

CPC分类号： G06F13/28

摘要： A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

摘要翻译： 系统和方法将来自单线程应用程序的信息通过多个I / O总线传送到计算子系统进行处理。 根据一个实施例，提供了一种方法，其将用于与计算机子系统进行通信的状态顺序信息分开，通过多个输入/输出总线将分区信息传送到子系统，并且分别处理在多个输入/输出总线中接收的信息 的输入/输出总线，没有首先对信息进行排序。

公开(公告)号：US06313839B1

公开(公告)日：2001-11-06

申请号：US09178525

申请日：1998-10-23

申请人： Ronald D. Larson

发明人： Ronald D. Larson

IPC分类号： G06F1500

CPC分类号： G06T15/405

摘要： A method and apparatus is provided for performing Z depth comparison tests in a computer graphics display system. The minimum and maximum Z values are calculated for each region of Z values stored in a Z buffer memory device. When a Z value to be tested is received, the Z value is tested against the maximum Z value to determine whether the primitive is occluded. The maximum Z value corresponds to the largest Z value of a region of Z values. The minimum Z value corresponds to the smallest Z value of all of the Z values of the region. If a determination is made that the primitive is not occluded, the received Z value is tested against the minimum Z value. If a determination is made that the received Z value is less than the minimum Z value, the received Z value is retained and is ultimately stored in the Z buffer memory element. The minimum and maximum Z values are updated using the Z values which are contained in the Z buffer memory element. The depth comparison tests may be performed in a frame buffer controller of a computer graphics display system. The controller may comprise a cache memory element for storing a region of Z values and the maximum and minimum Z values associated with the region used in the depth comparison tests. By using the cache memory device in this manner, the number of reads from the Z buffer memory device is reduced.

摘要翻译： 提供了一种用于在计算机图形显示系统中执行Z深度比较测试的方法和装置。 对存储在Z缓冲存储器件中的Z值的每个区域计算最小和最大Z值。 当接收到要测试的Z值时，根据最大Z值测试Z值，以确定原语是否被遮挡。 最大Z值对应于Z值区域的最大Z值。 最小Z值对应于该区域的所有Z值的最小Z值。 如果确定原语未被遮挡，则根据最小Z值测试收到的Z值。 如果确定接收的Z值小于最小Z值，则接收的Z值被保留并最终存储在Z缓冲存储器元件中。 使用包含在Z缓冲存储器元件中的Z值来更新最小和最大Z值。 深度比较测试可以在计算机图形显示系统的帧缓冲器控制器中执行。 控制器可以包括高速缓冲存储器元件，用于存储Z值的区域以及与深度比较测试中使用的区域相关联的最大和最小Z值。 通过以这种方式使用高速缓冲存储器件，减少了来自Z缓冲存储器件的读取次数。