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5 条记录 (耗时 0.022 秒)

    Tuneable ferroelectric decoupling capacitor
    1.
    发明授权
    Tuneable ferroelectric decoupling capacitor 有权
    可调铁电去耦电容器

    公开(公告)号：US06507476B1

    公开(公告)日：2003-01-14

    申请号：US09430901

    申请日：1999-11-01

    申请人： Thomas M. Shaw ,  W. David Pricer ,  Deborah A. Neumayer ,  John D. Baniecki ,  Robert B. Laibowitz

    发明人： Thomas M. Shaw ,  W. David Pricer ,  Deborah A. Neumayer ,  John D. Baniecki ,  Robert B. Laibowitz

    IPC分类号： H01G400

    CPC分类号： H01L27/0805 ,  H01L28/55

    摘要： A method for configuring a bypass capacitor for use in conjunction with an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.

    摘要翻译： 公开了一种用于配置与集成电路器件一起使用的旁路电容器的方法。 在本发明的示例性实施例中，该方法包括选择旁路电容器的机械尺寸，使得旁路电容器在集成电路器件的时钟频率处呈现电损耗的机械尺寸。 旁路电容器优选地包括铁电介质材料。 另外，旁路电容器的机械尺寸的选择决定了旁路电容器的机械共振频率，机械共振频率对应于时钟频率。

    Method for novel SOI DRAM BICMOS NPN
    3.
    发明授权
    Method for novel SOI DRAM BICMOS NPN 失效
    新型SOI DRAM BICMOS NPN的方法

    公开(公告)号：US06492211B1

    公开(公告)日：2002-12-10

    申请号：US09656819

    申请日：2000-09-07

    申请人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  G11C7/065 ,  G11C2207/005 ,  G11C2207/065 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/10897 ,  H01L27/1203

    摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

    摘要翻译： 在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。 使用NFET的DRAM阵列允许集成双极NPN序列。 类似地，通过将​​阵列晶体管改变为PFET来实现垂直双极PNP器件。 特别地，在SOI中制造BICMOS器件。 双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

    Broadband dc amplifier technique with very low offset voltage
    4.
    发明授权
    Broadband dc amplifier technique with very low offset voltage 失效
    宽带直流放大器技术具有非常低的失调电压

    公开(公告)号：US6034568A

    公开(公告)日：2000-03-07

    申请号：US97484

    申请日：1998-06-15

    申请人： Anthony R. Bonaccio ,  Michel S. Michail ,  W. David Pricer

    发明人： Anthony R. Bonaccio ,  Michel S. Michail ,  W. David Pricer

    IPC分类号： H03F1/48 ,  H03F3/45

    CPC分类号： H03F1/483

    摘要： An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.

    摘要翻译： 具有两个差分输入级的运算放大器用于分别实现低失调电压和宽带宽特性。 一个输入级用于解决直流和低频信号，而其他输入级则处理宽带频率。 形成直流级的所有晶体管都被偏置在子阈值区域中。 在两个差分输入级之后，信号路径在电容交叉网络中重新组合，提供用于后续放大的输出。 交叉频率的交叉电容可以使用小的实际值从15 kHz到50 kHz进行交叉。 两个输入级之间的增益平衡可通过运算放大器晶体管的电阻和/或预定的宽度/长度比来调节。

    Time standard circuit with delay line oscillator
    5.
    发明授权
    Time standard circuit with delay line oscillator 失效
    具延时线振荡器的时间标准电路

    公开(公告)号：US5673005A

    公开(公告)日：1997-09-30

    申请号：US516852

    申请日：1995-08-18

    申请人： W. David Pricer

    发明人： W. David Pricer

    IPC分类号： H03B5/20 ,  H03K3/03 ,  H03K5/14 ,  H03L7/081 ,  H03K5/13 ,  H03L7/00

    CPC分类号： H03L7/081 ,  H03B5/20 ,  H03K3/03 ,  H03K5/14

    摘要： This is an integrated timing circuit which can be formed on a microprocessor chip. The circuit uses an oscillator having a delay line and a variable delay element. The delay line and the delay element vary together to hold the velocity of signal propagation in the circuit substantially constant. The output, of the oscillator is coupled to one input of a comparator circuit. A series of inverter circuits, each of which has a respective variable delay are connected to the input of the oscillator and to a second input of the comparator circuit such that the comparator circuit senses the difference between the output signal of the inverter series and the output signal of the oscillator circuit to provide an error signal proportional to the sensed difference. A feedback loop is provided, to the variable delay means in said oscillator and to the inverter circuits to correct for the sensed difference, to establish a uniform and stable time standard at the output of the oscillator.

    摘要翻译： 这是一个可以在微处理器芯片上形成的集成定时电路。 该电路使用具有延迟线和可变延迟元件的振荡器。 延迟线和延迟元件一起变化以保持电路中的信号传播速度基本恒定。 振荡器的输出耦合到比较器电路的一个输入端。 每个具有各自可变延迟的逆变器电路连接到振荡器的输入端和比较器电路的第二输入端，使得比较器电路感测到逆变器系列的输出信号与输出 振荡器电路的信号，以提供与感测到的差异成比例的误差信号。 向所述振荡器中的可变延迟装置和反相器电路提供反馈回路以校正感测到的差异，以在振荡器的输出端建立均匀且稳定的时间标准。