Cache based physical layer self test
    4.
    发明申请
    Cache based physical layer self test 有权
    基于缓存的物理层自检

    公开(公告)号:US20060005092A1

    公开(公告)日:2006-01-05

    申请号:US10882966

    申请日:2004-06-30

    IPC分类号: G01R31/28

    CPC分类号: G06F11/27

    摘要: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

    摘要翻译: 从处理器的缓存执行软件自检引擎。 使用处理器的执行引擎执行软件自检引擎,以执行物理层自检。 通过在自检引擎的控制下将来自执行引擎的测试向量发送到处理器的输入/输出(“I / O”)单元,沿着将执行引擎耦合到I / O的数据通路执行物理层自检, O单位。 测试向量沿着包括I / O单元和数据通路的环回路径传输,以沿着循环路径测试硬件设备。