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公开(公告)号：US06992002B2
公开(公告)日：2006-01-31
申请号：US10305644
申请日：2002-11-26
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.
摘要翻译： 一种在半导体器件中使用的互连结构，其通过在金属层中引入形状的空隙来互连多个不同的金属布线层，这些不同的金属布线层是连接的通孔。 本发明还公开了一种构建这种结构的方法。
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公开(公告)号：US07498250B2
公开(公告)日：2009-03-03
申请号：US11837768
申请日：2007-08-13
IPC分类号： H01L21/44
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译： 互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。 互连结构包括具有电介质填充孔图案的镶嵌金属线。
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公开(公告)号：US06528883B1
公开(公告)日：2003-03-04
申请号：US09670411
申请日：2000-09-26
IPC分类号： H01L2348
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.
摘要翻译： 一种在半导体器件中使用的互连结构，其通过在金属层中引入形状的空隙来互连多个不同的金属布线层，这些不同的金属布线层是连接的通孔。 本发明还公开了一种构建这种结构的方法。
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公开(公告)号：US07709967B2
公开(公告)日：2010-05-04
申请号：US11837723
申请日：2007-08-13
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译： 互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。 互连结构包括具有电介质填充孔图案的镶嵌金属线。
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公开(公告)号：US07312141B2
公开(公告)日：2007-12-25
申请号：US11256025
申请日：2005-10-21
IPC分类号： H01L21/44
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译： 互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。 互连结构包括具有电介质填充孔图案的镶嵌金属线。
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公开(公告)号：US07685544B2
公开(公告)日：2010-03-23
申请号：US11947254
申请日：2007-11-29
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的计算机程序产品。 程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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公开(公告)号：US07051307B2
公开(公告)日：2006-05-23
申请号：US10707286
申请日：2003-12-03
申请人： Gary S. Ditlow , Daria R. Dooling , Timothy G. Dunham , William C. Leipold , Stephen D. Thomas , Ralph J. Williams
发明人： Gary S. Ditlow , Daria R. Dooling , Timothy G. Dunham , William C. Leipold , Stephen D. Thomas , Ralph J. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.
摘要翻译： 公开了通过基于设计层级中的逻辑宏的大小启发式来识别集成电路设计中的逻辑块来分割集成电路设计的方法和结构。 本发明确定逻辑块的数量是否在期望数量的逻辑块的范围内，并重复识别用于集成电路设计的不同层级的逻辑块的处理，直到逻辑块的数量在所需数量的范围内 的逻辑块。 这作为分配芯片的指南，而不是格栅分割。
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8.发明授权System and method for testing pattern sensitive algorithms for semiconductor design 失效用于半导体设计测试模式敏感算法的系统和方法公开(公告)号：US08201132B2
公开(公告)日：2012-06-12
申请号：US12631899
申请日：2009-12-07
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的系统和方法。 该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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9.发明申请SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN 失效用于测试半导体设计的模式敏感算法的系统和方法公开(公告)号：US20100095254A1
公开(公告)日：2010-04-15
申请号：US12631899
申请日：2009-12-07
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的系统和方法。 该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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10.发明授权System and method for testing pattern sensitive algorithms for semiconductor design 有权用于半导体设计测试模式敏感算法的系统和方法公开(公告)号：US07353472B2
公开(公告)日：2008-04-01
申请号：US11202591
申请日：2005-08-12
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的系统和方法。 该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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