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    Trilayer resist scheme for gate etching applications
    3.
    发明授权
    Trilayer resist scheme for gate etching applications 失效
    栅极蚀刻应用的三层抗蚀剂方案

    公开(公告)号：US07435671B2

    公开(公告)日：2008-10-14

    申请号：US11506227

    申请日：2006-08-18

    申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

    摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

    摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

    Trilayer resist scheme for gate etching applications
    6.
    发明申请
    Trilayer resist scheme for gate etching applications 失效

    公开(公告)号：US20080045011A1

    公开(公告)日：2008-02-21

    申请号：US11506227

    申请日：2006-08-18

    申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

    摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

    Trilayer resist scheme for gate etching applications
    8.
    发明授权
    Trilayer resist scheme for gate etching applications 有权
    栅极蚀刻应用的三层抗蚀剂方案

    公开(公告)号：US08084825B2

    公开(公告)日：2011-12-27

    申请号：US12245946

    申请日：2008-10-06

    申请人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Timothy J. Dalton ,  Ying Zhang

    IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L20/10

    CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/28123

    摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

    摘要翻译： 提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。 根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。 本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅 ，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY
    10.
    发明申请
    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY 审中-公开
    双重DAMASCENE工艺流程启用最小ULK膜修改和增强堆叠完整性

    公开(公告)号：US20090014880A1

    公开(公告)日：2009-01-15

    申请号：US12236809

    申请日：2008-09-24

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。