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    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY
    1.
    发明申请
    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY 审中-公开
    双重DAMASCENE工艺流程启用最小ULK膜修改和增强堆叠完整性

    公开(公告)号：US20090014880A1

    公开(公告)日：2009-01-15

    申请号：US12236809

    申请日：2008-09-24

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
    2.
    发明授权
    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity 失效
    双镶嵌工艺流程可实现极少的ULK膜修饰和增强的堆叠完整性

    公开(公告)号：US07435676B2

    公开(公告)日：2008-10-14

    申请号：US11328981

    申请日：2006-01-10

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME
    5.
    发明申请
    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 审中-公开
    具有部分自对准VIAS的互连结构及其生产方法

    公开(公告)号：US20090200683A1

    公开(公告)日：2009-08-13

    申请号：US12030756

    申请日：2008-02-13

    申请人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    发明人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.

    摘要翻译： 具有部分自对准的通孔的互连结构，其中在衬底上具有层间电介质层，其包含至少两条横穿平行于衬底的导电金属线和至少两个与衬底正交的导电金属通孔。 一种通过在衬底上沉积层间电介质层来生产自对准通孔的方法，将至少一个硬掩模沉积到层间电介质层上，以光刻方式形成具有细长通孔特征的通孔图案，并以任何顺序光刻形成线图案，然后 只要图案重叠以形成自对准的通孔特征，沉积导电金属和对应于该线的通孔特征的填充区域，首先将线图案首先转移到层间介质层形成线的特征中或者将该通孔图案转移到层间电介质层中 并且从线和通孔特征平坦化和去除多余的金属。