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公开(公告)号：US20250133741A1
公开(公告)日：2025-04-24
申请号：US18597801
申请日：2024-03-06
Applicant: Tokyo Electron Limited
Inventor： Partha MUKHOPADHYAY , Henry Jim FULFORD , Mark I. GARDNER
Abstract: A semiconductor device includes a first gate structure, a second gate structure, and a semiconductor layer. The first gate structure, the semiconductor layer, and the second gate structure are arranged concentrically. The first gate structure includes a first gate electrode and a ferroelectric layer. The second gate structure includes a second gate electrode and a gate dielectric layer. The semiconductor layer is disposed between the ferroelectric layer and the gate dielectric layer.
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公开(公告)号：US20250169178A1
公开(公告)日：2025-05-22
申请号：US18597779
申请日：2024-03-06
Applicant: Tokyo Electron Limited
Inventor： Mark I. GARDNER , Henry Jim FULFORD
Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device may include a semiconductor substrate including a first area and a second area; a first semiconductor structure disposed in the first area, vertically extending, and separated from the semiconductor substrate with a first dielectric structure interposed therebetween; a first transistor disposed around the first semiconductor structure, with the first semiconductor structure serving as a channel of the first transistor; a second semiconductor structure disposed in the second area, vertically extending, and in contact with the semiconductor substrate; and a second transistor disposed above the second semiconductor structure, with a third semiconductor structure laterally extending and serving as a channel of the second transistor.
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公开(公告)号：US20250040202A1
公开(公告)日：2025-01-30
申请号：US18227059
申请日：2023-07-27
Applicant: Tokyo Electron Limited
Inventor： Mark I. GARDNER , Henry Jim FULFORD
IPC: H01L29/06 , H01L27/092 , H01L29/10 , H01L29/66 , H01L29/786
Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The devices may include a first epitaxial structure disposed below a dielectric pillar, a second epitaxial structure disposed above the first epitaxial structure and around the dielectric pillar, a third epitaxial structure disposed above the second epitaxial structure and around the dielectric pillar, and a fourth epitaxial structure disposed above the third epitaxial structure and around the dielectric pillar. The second and third epitaxial structures may each have a portion inwardly extending toward a central axis of the dielectric pillar.
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公开(公告)号：US20250133743A1
公开(公告)日：2025-04-24
申请号：US18598907
申请日：2024-03-07
Applicant: Tokyo Electron Limited
Inventor： Partha MUKHOPADHYAY , Henry Jim FULFORD , Mark I. GARDNER
IPC: H10B51/30
Abstract: FeFET memory devices are provided. A semiconductor device includes a first metal structure of a first gate electrode. The semiconductor device includes a gate dielectric structure extending along a bottom surface of the first metal structure and surrounding a sidewall of the first metal structure. The semiconductor device includes a semiconductor-behaving structure extending along a bottom surface of the gate dielectric structure and surrounding a sidewall of the gate dielectric structure. The semiconductor device includes a ferroelectric structure surrounding a sidewall of the semiconductor-behaving structure. The semiconductor device includes a second gate electrode comprising a second metal structure in contact with the semiconductor-behaving structure.
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Patent Agency Ranking
公开(公告)号：US20250098174A1
公开(公告)日：2025-03-20
申请号：US18598660
申请日：2024-03-07
Applicant: Tokyo Electron Limited
Inventor： Partha MUKHOPADHYAY , Henry Jim FULFORD , Mark I. GARDNER
IPC: H10B51/30
Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first metal structure extending in a first lateral direction. The semiconductor device includes a first ferroelectric layer surrounding a first portion of the first metal structure. The semiconductor device includes a first channel layer surrounding the first ferroelectric layer. The semiconductor device includes a first gate structure surrounding the first portion of the first metal structure, with the first ferroelectric layer and the first channel layer interposed therebetween. The semiconductor device includes a first gate electrode in electrical contact with the first gate structure. The semiconductor device includes a second gate electrode in electrical contact with a second portion of the first metal structure.
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公开(公告)号：US20250031400A1
公开(公告)日：2025-01-23
申请号：US18224940
申请日：2023-07-21
Applicant: Tokyo Electron Limited
Inventor： Mark I. GARDNER , Henry Jim FULFORD , Partha MUKHOPADHYAY
IPC: H01L29/775 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/66 , H10B51/20
Abstract: A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.
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公开(公告)号：US20250123090A1
公开(公告)日：2025-04-17
申请号：US18485762
申请日：2023-10-12
Applicant: Tokyo Electron Limited
Inventor： Daniel FULFORD , Mark I. GARDNER , Henry Jim FULFORD , Anton DEVILLIERS
IPC: G01B7/28
Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.
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公开(公告)号：US20250098188A1
公开(公告)日：2025-03-20
申请号：US18597762
申请日：2024-03-06
Applicant: Tokyo Electron Limited
Inventor： Henry Jim FULFORD , Mark I. GARDNER
Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming vertical channel structures on a substrate. The vertical channel structures are formed within a layer stack of alternating layers of a first metal and a first dielectric. The vertical channel structures are channels of field effect transistors that have a current flow path perpendicular to a surface of the substrate. The vertical channel structures have a dielectric core. The method includes forming openings on the substrate that uncover a region of the layer stack adjacent to the vertical channel structures. The method includes, for each vertical channel structure, forming a corresponding staircase region in the layer stack, and forming metal contacts within each staircase region.
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公开(公告)号：US20250056810A1
公开(公告)日：2025-02-13
申请号：US18448086
申请日：2023-08-10
Applicant: Tokyo Electron Limited
Inventor： Henry Jim FULFORD , Mark I. GARDNER , Partha MUKHOPADHYAY
IPC: H10B53/30
Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first semiconductor structure extending along a vertical direction; a high-k dielectric layer disposed around at least the first semiconductor structure; a first metal structure disposed around the first semiconductor structure, with the high-k dielectric layer interposed therebetween; a ferroelectric structure disposed around the first semiconductor structure, with the high-k dielectric layer and the first metal structure interposed therebetween; and a second metal structure having a portion disposed around the first semiconductor structure, with the high-k dielectric layer, the first metal structure, and the ferroelectric structure interposed therebetween.
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