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    METHOD FOR PATTERN REDUCTION USING A STAIRCASE SPACER
    1.
    发明申请
    METHOD FOR PATTERN REDUCTION USING A STAIRCASE SPACER 有权

    公开(公告)号：US20210366714A1

    公开(公告)日：2021-11-25

    申请号：US17325789

    申请日：2021-05-20

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Anton J. DEVILLIERS

    IPC: H01L21/033 ,  H01L21/027

    Abstract: Devices are made by self-aligned quad pitch patterning (SAQP) and methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. An initial pattern is obtained by the X-Y double line exposures. Reverse material is applied on the initial pattern and subsequent etching process converts each initial trench pattern to a line. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.

    METHOD FOR TUNING STRESS TRANSITIONS OF FILMS ON A SUBSTRATE
    2.
    发明申请
    METHOD FOR TUNING STRESS TRANSITIONS OF FILMS ON A SUBSTRATE 有权

    公开(公告)号：US20210020435A1

    公开(公告)日：2021-01-21

    申请号：US16922809

    申请日：2020-07-07

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3105

    Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.

    DEVICE AND METHOD FOR DETERMINING WAFER BOW
    3.
    发明申请
    DEVICE AND METHOD FOR DETERMINING WAFER BOW 有权

    公开(公告)号：US20250123090A1

    公开(公告)日：2025-04-17

    申请号：US18485762

    申请日：2023-10-12

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  Henry Jim FULFORD ,  Anton DEVILLIERS

    IPC: G01B7/28

    Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

    DEVICE AND METHOD FOR DETERMINING WAFER BOW
    5.
    发明申请
    DEVICE AND METHOD FOR DETERMINING WAFER BOW 有权

    公开(公告)号：US20250167023A1

    公开(公告)日：2025-05-22

    申请号：US18511448

    申请日：2023-11-16

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/67 ,  G01B7/14 ,  H01L21/66 ,  H01L21/687

    Abstract: An apparatus for measuring bow of a wafer includes a substrate holder including a support surface configured to support a wafer, and an air flow system including a plurality of air outlets in the support surface which are configured to output air for elevating the wafer above the substrate holder. A capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit, each electrode facing the support surface and being spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a wafer elevated by the substrate holder.

    METHOD FOR PATTERN REDUCTION USING A STAIRCASE SPACER
    6.
    发明申请
    METHOD FOR PATTERN REDUCTION USING A STAIRCASE SPACER 有权

    公开(公告)号：US20210366713A1

    公开(公告)日：2021-11-25

    申请号：US17325425

    申请日：2021-05-20

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Anton J. DEVILLIERS

    IPC: H01L21/033 ,  H01L21/027

    Abstract: Devices are made by self-aligned quad pitch patterning (SAQP), staircase patterning and double staircase patterning. Methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. Methods for making devices by staircase patterning and double staircase patterning do not use a spacer. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.

    METHOD FOR PLANARIZATION OF ORGANIC FILMS
    8.
    发明申请
    METHOD FOR PLANARIZATION OF ORGANIC FILMS 审中-公开

    公开(公告)号：US20200152472A1

    公开(公告)日：2020-05-14

    申请号：US16674790

    申请日：2019-11-05

    Applicant: Tokyo Electron Limited

    Inventor： Anton DEVILLIERS ,  Robert BRANDT ,  Jeffrey SMITH ,  Jodi GRZESKOWIAK ,  Daniel FULFORD

    IPC: H01L21/3105 ,  H01L21/027 ,  G03F7/004 ,  G03F7/09 ,  G03F7/38 ,  G03F7/16 ,  G03F7/32 ,  G03F7/20

    Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.

    WAFER SUPPORT FOR MEASURING WAFER GEOMETRY
    9.
    发明申请
    WAFER SUPPORT FOR MEASURING WAFER GEOMETRY 有权

    公开(公告)号：US20250167024A1

    公开(公告)日：2025-05-22

    申请号：US18511557

    申请日：2023-11-16

    Applicant: Tokyo Electron Limited

    Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD

    IPC: H01L21/67 ,  G01B21/20 ,  H01L21/66

    Abstract: A wafer measurement stage for supporting a semiconductor wafer for surface geometry measurements. The wafer measurement stage includes a support body having a planar surface configured to face a wafer which is supported by the wafer measurement stage, and a wafer contact structure provided on the planar surface. The wafer contact structure is configured to contact a portion of a wafer such that the wafer is supported in an elevated position relative to the planar surface and to control gravity effects at non-contact portions of the wafer.

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