公开(公告)号：US20240203797A1

公开(公告)日：2024-06-20

申请号：US18081207

申请日：2022-12-14

Applicant: Tokyo Electron Limited

Inventor： Andrew WELOTH ,  Daniel FULFORD ,  Anthony SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS ,  David CONKLIN

IPC: H01L21/66 ,  G03F7/00 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L22/20 ,  G03F7/0035 ,  H01L21/02002 ,  H01L21/67092 ,  H01L21/67288

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

公开(公告)号：US20210118798A1

公开(公告)日：2021-04-22

申请号：US16659251

申请日：2019-10-21

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Anton DEVILLIERS ,  Daniel CHANEMOUGAME

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

公开(公告)号：US20200303256A1

公开(公告)日：2020-09-24

申请号：US16898014

申请日：2020-06-10

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Subhadeep KAL ,  Anton DEVILLIERS

IPC: H01L21/822 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L27/06

Abstract: A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.

公开(公告)号：US20240203778A1

公开(公告)日：2024-06-20

申请号：US18085354

申请日：2022-12-20

Applicant: Tokyo Electron Limited

Inventor： David POWER ,  David CONKLIN ,  Anthony SCHEPIS ,  Andrew WELOTH ,  Anton DEVILLIERS

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/681 ,  H01L21/67265 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68363 ,  H01L2223/54426

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

公开(公告)号：US20230367217A1

公开(公告)日：2023-11-16

申请号：US18354388

申请日：2023-07-18

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anthony SCHEPIS ,  Anton DEVILLIERS

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/004 ,  G03F7/11

CPC classification number: G03F7/094 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  G03F7/0045 ,  H01L21/3088 ,  G03F7/11 ,  G03F7/091 ,  H01L21/3086

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US20230036597A1

公开(公告)日：2023-02-02

申请号：US17878457

申请日：2022-08-01

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Paul GUTWIN ,  Subhadeep KAL ,  Kandabara TAPILY ,  Anton DEVILLIERS

IPC: H01L21/822 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

公开(公告)号：US20150044785A1

公开(公告)日：2015-02-12

申请号：US14453352

申请日：2014-08-06

Applicant: Tokyo Electron Limited

Inventor： Carlos A. FONSECA ,  Anton DEVILLIERS ,  Benjamen M. RATHSACK ,  Jeffrey T. SMITH ,  Lior HULI

IPC: H01L21/66 ,  H01L21/306

CPC classification number: H01L21/02016 ,  G03F7/70783 ,  H01L21/30625 ,  H01L21/687 ,  H01L22/12 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Abstract translation: 所描述的实施例涉及一种减小光刻畸变的方法和装置。 半导体衬底的背面可以被组织化。 然后可以在具有纹理化背面的半导体衬底上进行光刻工艺。

公开(公告)号：US20220122892A1

公开(公告)日：2022-04-21

申请号：US17392997

申请日：2021-08-03

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Paul GUTWIN ,  Robert CLARK ,  Anton DEVILLIERS

IPC: H01L21/8238 ,  H01L23/00 ,  H01L21/306 ,  H01L21/324

Abstract: Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.

公开(公告)号：US20220115271A1

公开(公告)日：2022-04-14

申请号：US17557561

申请日：2021-12-21

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/48 ,  H01L21/822 ,  H01L23/532

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

公开(公告)号：US20200266169A1

公开(公告)日：2020-08-20

申请号：US16782882

申请日：2020-02-05

Applicant: Tokyo Electron Limited

Inventor： Hoyoung KANG ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Anton DEVILLIERS ,  Daniel CHANEMOUGAME

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/321 ,  H01L21/308

Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.