公开(公告)号：US20240249978A1

公开(公告)日：2024-07-25

申请号：US18159462

申请日：2023-01-25

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L21/822 ,  H01L27/088

CPC classification number: H01L21/8221 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

公开(公告)号：US20230189514A1

公开(公告)日：2023-06-15

申请号：US17546785

申请日：2021-12-09

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/11556 ,  H01L27/06 ,  H01L21/822 ,  H01L29/786

CPC classification number: H01L27/11556 ,  H01L27/0688 ,  H01L21/8221 ,  H01L29/78696

Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.

公开(公告)号：US20230128495A1

公开(公告)日：2023-04-27

申请号：US17742893

申请日：2022-05-12

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L29/423 ,  H01L27/06 ,  H01L21/8258 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/22 ,  H01L29/24

Abstract: A semiconductor device includes a stack of transistors stacked over a base in a direction substantially perpendicular to a working surface of the base. Each transistor includes a respective channel structure, respective source/drain (S/D) regions positioned on ends of the respective channel structure, and a respective gate structure disposed all around the respective channel structure. Each channel structure includes a respective non-epitaxial compound semiconductor.

公开(公告)号：US20250133741A1

公开(公告)日：2025-04-24

申请号：US18597801

申请日：2024-03-06

Applicant: Tokyo Electron Limited

Inventor： Partha MUKHOPADHYAY ,  Henry Jim FULFORD ,  Mark I. GARDNER

IPC: H10B51/20 ,  H10B51/30

Abstract: A semiconductor device includes a first gate structure, a second gate structure, and a semiconductor layer. The first gate structure, the semiconductor layer, and the second gate structure are arranged concentrically. The first gate structure includes a first gate electrode and a ferroelectric layer. The second gate structure includes a second gate electrode and a gate dielectric layer. The semiconductor layer is disposed between the ferroelectric layer and the gate dielectric layer.

公开(公告)号：US20230301059A1

公开(公告)日：2023-09-21

申请号：US17959771

申请日：2022-10-04

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally; an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally; a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor, the lower metal capacitor including a first lower metal plate, a lower dielectric layer that surrounds the first lower metal plate, and a second lower metal plate that surrounds the lower dielectric layer; and an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor, the upper metal capacitor including a first upper metal plate, an upper dielectric layer that surrounds the first upper metal plate, and a second upper metal plate that surrounds the upper dielectric layer.

公开(公告)号：US20230261113A1

公开(公告)日：2023-08-17

申请号：US18093205

申请日：2023-01-04

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088 ,  H01L25/065 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/78618 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  H01L27/088 ,  H01L25/0657 ,  H01L21/762 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877

Abstract: A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.

公开(公告)号：US20230207660A1

公开(公告)日：2023-06-29

申请号：US17957076

申请日：2022-09-30

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/66439 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/76251 ,  H01L29/401

Abstract: A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a first surface of a semiconductor device layer; and forming a second SD contact layer on a second surface of the semiconductor device layer, the second surface being opposite to the first surface. The semiconductor device layer is pattern etched to form a vertical channel structure having a first end connected to the first SD contact and a second end opposite to the first end and connected to the second SD contact. A gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure at a position between the first SD contact and the second SD contact.

公开(公告)号：US20250133743A1

公开(公告)日：2025-04-24

申请号：US18598907

申请日：2024-03-07

Applicant: Tokyo Electron Limited

Inventor： Partha MUKHOPADHYAY ,  Henry Jim FULFORD ,  Mark I. GARDNER

IPC: H10B51/30

Abstract: FeFET memory devices are provided. A semiconductor device includes a first metal structure of a first gate electrode. The semiconductor device includes a gate dielectric structure extending along a bottom surface of the first metal structure and surrounding a sidewall of the first metal structure. The semiconductor device includes a semiconductor-behaving structure extending along a bottom surface of the gate dielectric structure and surrounding a sidewall of the gate dielectric structure. The semiconductor device includes a ferroelectric structure surrounding a sidewall of the semiconductor-behaving structure. The semiconductor device includes a second gate electrode comprising a second metal structure in contact with the semiconductor-behaving structure.

公开(公告)号：US20250098174A1

公开(公告)日：2025-03-20

申请号：US18598660

申请日：2024-03-07

Applicant: Tokyo Electron Limited

Inventor： Partha MUKHOPADHYAY ,  Henry Jim FULFORD ,  Mark I. GARDNER

IPC: H10B51/30

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first metal structure extending in a first lateral direction. The semiconductor device includes a first ferroelectric layer surrounding a first portion of the first metal structure. The semiconductor device includes a first channel layer surrounding the first ferroelectric layer. The semiconductor device includes a first gate structure surrounding the first portion of the first metal structure, with the first ferroelectric layer and the first channel layer interposed therebetween. The semiconductor device includes a first gate electrode in electrical contact with the first gate structure. The semiconductor device includes a second gate electrode in electrical contact with a second portion of the first metal structure.

公开(公告)号：US20250031400A1

公开(公告)日：2025-01-23

申请号：US18224940

申请日：2023-07-21

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  Henry Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H10B51/20

Abstract: A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.