公开(公告)号：US08363496B2

公开(公告)日：2013-01-29

申请号：US12805238

申请日：2010-07-20

申请人： Tomonori Hayashi ,  Akihiko Kagami ,  Yuji Sugiyama

发明人： Tomonori Hayashi ,  Akihiko Kagami ,  Yuji Sugiyama

IPC分类号： G11C29/08 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/50016

摘要： A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.

摘要翻译： 一种半导体存储器件，包括掩模信息存储电路，其存储指示在存储单元阵列中的多个区域中表示不进行自刷新操作的区域的掩模信息，由自刷新命令激活的掩模确定电路 并且响应于刷新地址和掩模信息之间的匹配的检测而产生匹配信号，以及响应于匹配信号的激活而禁用自刷新操作的刷新操作控制电路。 当测试模式信号被激活时，掩模确定电路也被自动刷新命令激活。 利用这种配置，可以在不实际进入自刷新模式的情况下执行部分阵列自刷新功能的测试。

公开(公告)号：US20110026339A1

公开(公告)日：2011-02-03

申请号：US12805238

申请日：2010-07-20

申请人： Tomonori Hayashi ,  Akihiko Kagami ,  Yuji Sugiyama

发明人： Tomonori Hayashi ,  Akihiko Kagami ,  Yuji Sugiyama

IPC分类号： G11C29/08 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/50016

摘要： A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.

摘要翻译： 一种半导体存储器件，包括掩模信息存储电路，其存储指示在存储单元阵列中的多个区域中表示不进行自刷新操作的区域的掩模信息，由自刷新命令激活的掩模确定电路 并且响应于刷新地址和掩模信息之间的匹配的检测而产生匹配信号，以及响应于匹配信号的激活而禁用自刷新操作的刷新操作控制电路。 当测试模式信号被激活时，掩模确定电路也被自动刷新命令激活。 利用这种配置，可以在不实际进入自刷新模式的情况下执行部分阵列自刷新功能的测试。

公开(公告)号：US07606094B2

公开(公告)日：2009-10-20

申请号：US11781757

申请日：2007-07-23

申请人： Masski Seno ,  Akihiko Kagami

发明人： Masski Seno ,  Akihiko Kagami

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/065

摘要： A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference appearing on a bit line pair; a power supply line pair including first and second power supply lines for supplying first and second potentials to the sense amplifier; a pre-charge power supply line for supplying a predetermined pre-charge potential; a power supply line equalize circuit for setting the first and second potentials at the same potential based on the pre-charge potential; a current limit circuit inserted in series in a predetermined current path from the pre-charge power supply line to the power supply line pair; and switch means capable of switching whether or not current flowing from the pre-charge power supply line to the power supply line pair is limited by the current limit circuit based on a control signal.

摘要翻译： 本发明的半导体存储器件具有布置在位线和字线的交点处的存储单元，并且包括用于放大出现在位线对上的微小电位差的读出放大器; 电源线对，包括用于向读出放大器提供第一和第二电位的第一和第二电源线; 用于提供预定预充电电位的预充电电源线; 电源线均衡电路，用于基于预充电电位将第一和第二电位设置在相同的电位; 电流限制电路串联插入到从预充电电源线到电源线对的预定电流路径中; 以及能够切换从预充电电源线流到电源线对的电流是否受到基于控制信号的限流电路的限制的开关装置。

公开(公告)号：US5940331A

公开(公告)日：1999-08-17

申请号：US143382

申请日：1998-08-28

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  H01L27/06 ,  G11C16/04

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106

摘要： An output circuit of a semiconductor memory device is provided, which prevents a current from flowing through a pair of output transistors due to their ON-ON state. This output circuit is comprised of (a) first and second transfer gates for receiving first and second complementary read-bus data signals and for transferring the first and second read-bus data signals according to a transfer-gate control signal, (b) first and second latches for latching the first and second read-bus data signals transferred to first and second nodes, respectively, (c) a precharge signal generator for generating a precharge signal to precharge the first and second nodes to a same electric potential, (d) first and second transistor drivers for outputting first and second driving signals according to the first and second read-bus data signals latched at the first and second nodes, respectively, and (e) first and second complementary output transistors driven by the first and second driving signals outputted from the first and second drivers, respectively. The first and second nodes are respectively precharged to the same electric potentials by the precharge signal before the complementary first and second read-bus data signals are transferred by the first and second transfer gates and latched by the first and second latches at the first and second nodes, respectively.

摘要翻译： 提供半导体存储器件的输出电路，其防止由于其导通状态而导致电流流过一对输出晶体管。 该输出电路包括：（a）用于接收第一和第二互补读总线数据信号的第一和第二传输门，以及根据传输门控制信号传送第一和第二读总线数据信号，（b）第一 以及第二锁存器，用于分别锁存传送到第一和第二节点的第一和第二读取总线数据信号;（c）预充电信号发生器，用于产生预充电信号，以将第一和第二节点预充电至相同的电位;（d ）第一和第二晶体管驱动器，用于分别根据在第一和第二节点处锁存的第一和第二读取总线数据信号输出第一和第二驱动信号，以及（e）由第一和第二驱动信号驱动的第一和第二互补输出晶体管 分别从第一和第二驱动器输出的驱动信号。 第一和第二节点在互补的第一和第二读总线数据信号由第一和第二传输门传输之前由预充电信号分别预充电到相同的电位，并由第一和第二锁存器在第一和第二锁存器处锁存 节点。

公开(公告)号：US5295099A

公开(公告)日：1994-03-15

申请号：US957057

申请日：1992-10-06

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/409 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096

摘要： A dynamic random access memory device comprises memory cells arranged in rows and columns and storing data bits, respectively, bit line pairs respectively coupled to every two columns of the memory cells for propagating the data bits read out from the memory cells, word lines respectively coupled to the rows of the memory cells and allowing the data bits stored in one of the rows of the memory cells to be read out to the bit line pairs, sense amplifier circuits provided in association with the bit line pairs and selectively coupling the component bit lines to first and second sources of voltage level depending upon the logic level of the data bits, a pair of data signal lines coupled to an output data buffer circuit, a column selector unit coupled between the bit line pairs and the data signal lines and sequentially interconnecting the bit line pairs and the data signal lines in a static column mode of operation, and a precharging unit coupled to the data signal lines and having current paths from the first source of voltage level to the data signal lines, wherein a limiter is coupled between the first source of voltage level and the data signal lines and prohibits the data signal lines from undesirable low voltage level so that any data bits on the bit line pairs are never destroyed.

摘要翻译： 动态随机存取存储器件包括以行和列排列并分别存储数据位的存储器单元，分别耦合到存储器单元的每两列的位线对，用于传播从存储器单元读出的数据位，分别耦合 到存储器单元的行中，并且将存储在存储单元的一行中的数据位读出到位线对，读出放大器电路，与位线对相关联地设置，并选择性地耦合分量位线 根据数据位的逻辑电平，耦合到输出数据缓冲电路的一对数据信号线，耦合在位线对和数据信号线之间的列选择器单元，并依次互连 位线对和数据信号线处于静态列操作模式，以及预充电单元，耦合到数据信号线并具有电流 t路径，从电压电平的第一源到数据信号线，其中限幅器耦合在第一电压电平源与数据信号线之间，并禁止数据信号线从不期望的低电压电平，使得任何数据位在 位线对不会被破坏。

公开(公告)号：US5394369A

公开(公告)日：1995-02-28

申请号：US010194

申请日：1993-01-28

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34 ,  G11C13/00

CPC分类号： G11C29/70 ,  G11C29/781

摘要： In a semiconductor memory device which can perform a parallel test upon a predetermined number of memory cells by using a degenerate address of a plurality of first addresses each corresponding to one memory cell, when a defective memory cell is found by a parallel test using the degenerate address, an address whose space includes the space of the degenerate address is written into only one location of its corresponding redundancy decoder to replace the defective memory cell with its corresponding redundancy memory cell.

摘要翻译： 在可以通过使用与一个存储单元相对应的多个第一地址的简并地址来对预定数量的存储单元执行并行测试的半导体存储器件中，当通过使用退化的并行测试发现有缺陷的存储单元时 地址，其空间包括简并地址的空间的地址仅写入其对应的冗余解码器的一个位置，以用相应的冗余存储单元替换有缺陷的存储单元。

公开(公告)号：US5091884A

公开(公告)日：1992-02-25

申请号：US543509

申请日：1990-06-26

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/835

摘要： For accelerating of a testing operation to determine which memory cell in a memory cell array is replaced with a redundant memory cell, a semiconductor memory device is composed of an address discriminating facility having an activation circuit operative to compare an address indicated by an address signal and the address assigned the memory cell replaced with the redundant memory cell for producing a first controlling signal. A testing operation controlling circuit is responsive to a test mode signal for producing a second controlling signal and a data write-in circuit responsive to the second controlling signal and producing a test bit of logic "1" level and a test bit of logic "0" level. The test bit of logic "1" and the test bit of logic "0" are respectively written into the redundant memory cell and the memory cell array so that an address assigned to the memory cell replaced with the redundant memory cell is discriminated through a read-out operation.

公开(公告)号：US4975881A

公开(公告)日：1990-12-04

申请号：US457900

申请日：1989-12-27

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/83

摘要： A semiconductor memory device having a redundant memory cell group selectable by a redundant decoder operable by a small power consumption is disclosed. The redundant decoder comprises a plurality of address program circuits which store address of a defective memory cell or cells and a control circuit for enabling the address program circuits when at least one defective memory cell is present and disenabling the address program circuits when no defective memory cell is present.

公开(公告)号：US20100128547A1

公开(公告)日：2010-05-27

申请号：US11996694

申请日：2006-07-19

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/40622

摘要： There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array (10) divided into a plurality of banks (0 to 3) each of which can be controlled independently and its peripheral circuit. Each of the banks 0 to 3 has a refresh counter (24) for generating a row address to be refreshed. A control circuit (20) executes refresh operation for the bank selected according to the bank selection data in accordance with a refresh request having bank selection data for selecting a plurality of banks 0 to 3 in an arbitrary combination. On the other hand, the control circuit (3) performs control no to execute refresh operation for the bank not selected according to the bank selection data. By performing such a refresh control, it is possible to rapidly perform each refresh operation by eliminating refresh of a bank in a busy state, there by improving the operation efficiency.

摘要翻译： 提供了一种半导体存储器件等，其具有优选的操作效率，并且在刷新分成多个存储体的存储器阵列时消除复杂的控制。 半导体存储器件包括被分成多个存储体（0至3）的存储器阵列（10），每个存储器阵列可独立地被控制并且其外围电路。 每个存储体0至3具有用于生成要刷新的行地址的刷新计数器（24）。 控制电路（20）根据具有用于以任意组合选择多个存储体0至3的存储体选择数据的刷新请求，根据存储体选择数据执行针对存储体的刷新操作。 另一方面，控制电路（3）对根据存储体选择数据未选择的存储体进行控制，不执行刷新操作。 通过执行这种刷新控制，可以通过提高操作效率，通过消除繁忙状态下的存储体的刷新来快速执行每个刷新操作。

公开(公告)号：US5629944A

公开(公告)日：1997-05-13

申请号：US670823

申请日：1996-06-25

申请人： Akihiko Kagami

发明人： Akihiko Kagami

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/46 ,  G11C29/56 ,  H01L21/66

CPC分类号： G11C29/46

摘要： A test mode setting circuit includes a high voltage detection circuit, an uppermost row address buffer and a row address buffer control circuit for the uppermost row address buffer. When a high voltage is supplied to a common input terminal for the test mode setting, the uppermost row address buffer receives through the common input terminal an uppermost address signal, and provides the uppermost address signal as an uppermost internal row address signal. The row address buffer control circuit operates such that, when an upper stage transistor in stacked two N-channel MOS transistors of the uppermost row address buffer becomes conductive through the high voltage, an internal control signal for the uppermost row address buffer is supplied to a lower stage transistor connected to a ground thus causing the lower stage transistor to become a non-conductive state whereby a voltage across the gate and source electrodes and a voltage across the gate and drain electrodes of the upper stage transistor are rendered to be a level lower than the high voltage. This enables the relaxing of the high electric field applied to the gate electrode and the reducing of the likelihood of the destruction of the gate oxide film.

摘要翻译： 测试模式设置电路包括高电压检测电路，最上行地址缓冲器和用于最上行地址缓冲器的行地址缓冲器控制电路。 当向测试模式设置的公共输入端子提供高电压时，最上面的行地址缓冲器通过公共输入端子接收最上面的地址信号，并将最上面的地址信号提供为最上面的内部行地址信号。 行地址缓冲器控制电路工作，使得当最高行地址缓冲器的堆叠的两个N沟道MOS晶体管的上级晶体管通过高电压变为导通时，用于最上面的行地址缓冲器的内部控制信号被提供给 下级晶体管连接到地，从而导致下级晶体管变为非导通状态，由此使栅极和源电极两端的电压以及上级晶体管的栅极和漏极两端的电压变为低电平 比高压。 这使得放电施加到栅电极的高电场和降低栅极氧化膜破坏的可能性。