公开(公告)号：US20120281985A1

公开(公告)日：2012-11-08

申请号：US13463136

申请日：2012-05-03

申请人： Hiroyuki HONMA ,  Masahiro Shioda ,  Toru Katagiri

发明人： Hiroyuki HONMA ,  Masahiro Shioda ,  Toru Katagiri

IPC分类号： H04J14/08

CPC分类号： H04J3/1652 ,  H04J2203/0089

摘要： A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.

摘要翻译： 发送装置包括帧分割电路，其基于预定的内部将帧周期彼此不同的多个帧的帧数据映射到具有固定帧周期和固定传输速率的一个或多个内部帧 时钟; 交叉连接电路，以内部时钟为单位，以时分复用系统中的各帧的帧数据交叉连接; 以及帧合成电路，其将多个帧中的任一个解映射或多路复用由交叉连接电路交叉连接的一个或多个内部帧的数据。

公开(公告)号：US08824507B2

公开(公告)日：2014-09-02

申请号：US13463136

申请日：2012-05-03

申请人： Hiroyuki Honma ,  Masahiro Shioda ,  Toru Katagiri

发明人： Hiroyuki Honma ,  Masahiro Shioda ,  Toru Katagiri

IPC分类号： H04J3/24 ,  H04J3/16

CPC分类号： H04J3/1652 ,  H04J2203/0089

摘要： A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.

摘要翻译： 发送装置包括帧分割电路，其基于预定的内部将帧周期彼此不同的多个帧的帧数据映射到具有固定帧周期和固定传输速率的一个或多个内部帧 时钟; 交叉连接电路，以内部时钟为单位，以时分复用系统中的各帧的帧数据交叉连接; 以及帧合成电路，其将多个帧中的任一个解映射或多路复用由交叉连接电路交叉连接的一个或多个内部帧的数据。

公开(公告)号：US20120230350A1

公开(公告)日：2012-09-13

申请号：US13400827

申请日：2012-02-21

申请人： Toru KATAGIRI ,  Masahiro Shioda

发明人： Toru KATAGIRI ,  Masahiro Shioda

IPC分类号： H04J14/00

CPC分类号： H04J3/1652

摘要： A signal demultiplexer includes a conversion unit that converts a format of a high speed signal transfer frame output from a terminating unit into a format of a converted frame; a parallelization unit that parallelizes the converted frame and outputs a predetermined number of data columns; and a separating unit that separates plural low speed signal transfer frames from the predetermined number of the data columns. The conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying a signal storing area using first and second overhead areas, to include an “i” th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area into an arbitrary “i” th data column among the predetermined number of the data columns, and to align front positions of the predetermined number of the data columns.

摘要翻译： 信号解复用器包括转换单元，其将从终端单元输出的高速信号传送帧的格式转换为转换帧的格式; 并行化单元，其并行化所转换的帧并输出预定数量的数据列; 以及分离单元，其从预定数量的数据列分离多个低速信号传送帧。 转换单元通过使用第一和第二开销区域延迟信号存储区域来将高速信号传送帧的格式转换为转换帧的格式，以在预定数量的辅助时隙中包括“第i个”支路时隙 分配给信号存储区域到预定数量的数据列中的任意“第i”个数据列，并且对准预定数量的数据列的前端位置。

公开(公告)号：US08687655B2

公开(公告)日：2014-04-01

申请号：US13400827

申请日：2012-02-21

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J3/24

CPC分类号： H04J3/1652

摘要： A signal demultiplexer includes a conversion unit that converts a format of a high speed signal transfer frame output from a terminating unit into a format of a converted frame; a parallelization unit that parallelizes the converted frame and outputs a predetermined number of data columns; and a separating unit that separates plural low speed signal transfer frames from the predetermined number of the data columns. The conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying a signal storing area using first and second overhead areas, to include an “i” th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area into an arbitrary “i” th data column among the predetermined number of the data columns, and to align front positions of the predetermined number of the data columns.

摘要翻译： 信号解复用器包括转换单元，其将从终端单元输出的高速信号传送帧的格式转换为转换帧的格式; 并行化单元，其并行化所转换的帧并输出预定数量的数据列; 以及分离单元，其从预定数量的数据列分离多个低速信号传送帧。 转换单元通过使用第一和第二开销区域延迟信号存储区域来将高速信号传送帧的格式转换为转换帧的格式，以在预定数量的辅助时隙中包括“第i个”支路时隙 分配给信号存储区域到预定数量的数据列中的任意“第i”个数据列，并且对准预定数量的数据列的前端位置。

公开(公告)号：US08675684B2

公开(公告)日：2014-03-18

申请号：US12719277

申请日：2010-03-08

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J3/24

CPC分类号： H04J3/076 ,  H04J3/1652 ,  H04J3/1664

摘要： A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.

摘要翻译： 以比客户端信号更高的比特率的光数据传输单元帧中容纳客户端信号的帧生成装置包括解串器，多个通用映射程序电路和串行器。 解串器将客户端信号反序列化为并行信号，对应于在光学数据传送单元帧中使用的支路数量的并行信号的数量。 多个通用映射程序电路基于客户端信号与光学数据传送单元帧之间的比特率的差异将数据和填充物插入到光学数据传送单元帧的帧容纳部分中。 串行器串行化从多个通用映射程序电路输出的并行信号。

公开(公告)号：US20130058643A1

公开(公告)日：2013-03-07

申请号：US13665146

申请日：2012-10-31

申请人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

发明人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

IPC分类号： H04B10/08

CPC分类号： H04J3/1652 ,  H04J2203/0058 ,  H04L43/0876

摘要： A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.

摘要翻译： 数据量导出装置包括：第一计算器，被配置为针对一系列并行映射信号，对并行映射信号映射到的帧的每个帧周期中的数据量; 以及第二计算器，被配置为对N个帧周期内的数据量进行相加，其中N是整数，并且导出所得到的求和值作为要映射到该帧中的数据量，每个数据量 帧周期由第一计算器导出。

公开(公告)号：US20100226648A1

公开(公告)日：2010-09-09

申请号：US12719277

申请日：2010-03-08

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J14/00 ,  H04B10/00

CPC分类号： H04J3/076 ,  H04J3/1652 ,  H04J3/1664

摘要： A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.

摘要翻译： 以比客户端信号更高的比特率的光数据传输单元帧中容纳客户端信号的帧生成装置包括解串器，多个通用映射程序电路和串行器。 解串器将客户端信号反序列化为并行信号，对应于在光学数据传送单元帧中使用的支路数量的并行信号的数量。 多个通用映射程序电路基于客户端信号与光学数据传送单元帧之间的比特率的差异将数据和填充物插入到光学数据传送单元帧的帧容纳部分中。 串行器串行化从多个通用映射程序电路输出的并行信号。

公开(公告)号：US07639702B2

公开(公告)日：2009-12-29

申请号：US11528370

申请日：2006-09-28

申请人： Hideki Matsui ,  Mitsuhiro Kawaguchi ,  Masahiro Shioda ,  Ryuji Kayama ,  Takashi Kaiga

发明人： Hideki Matsui ,  Mitsuhiro Kawaguchi ,  Masahiro Shioda ,  Ryuji Kayama ,  Takashi Kaiga

IPC分类号： H04L12/28

CPC分类号： H04J3/14 ,  H04J2203/0042 ,  H04J2203/006 ,  H04J2203/0085

摘要： A plug-in card for an optical transmission apparatus includes a J1generating unit. The J1 generating unit sends information on on-use side J1 data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 generating unit receives information on on-use side J1 data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 generating unit matches spare side J1 data to the on-use side J1 data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 generating unit does in processing B3 byte data.

摘要翻译： 一种用于光传输设备的插入式卡包括一个J1字节生成单元。 J1字节产生单元，当插件卡作为使用侧插件卡进行操作时，以冗余结构将关于使用侧J1字节数据的信息发送到备用侧的插入卡。 当插入卡作为备用插入卡操作时，J1字节生成单元从使用侧的插件卡接收关于使用侧J1字节数据的信息。 基于该信息，J1字节生成单元将备用侧J1字节数据与使用侧J1字节数据进行匹配。 该插入卡还包括一个B3字节计算单元，其操作方式与J1字节生成单元在处理B3字节数据时相似。

公开(公告)号：US20080037592A1

公开(公告)日：2008-02-14

申请号：US11780099

申请日：2007-07-19

申请人： Takashi Kaiga ,  Koichi Sugama ,  Tsutomu Chikazawa ,  Yukio Katayanagi ,  Kenichi Yajima ,  Hideo Abe ,  Ryuji Kayama ,  Masahiro Shioda

发明人： Takashi Kaiga ,  Koichi Sugama ,  Tsutomu Chikazawa ,  Yukio Katayanagi ,  Kenichi Yajima ,  Hideo Abe ,  Ryuji Kayama ,  Masahiro Shioda

IPC分类号： H04J3/06

CPC分类号： H04J3/0691 ,  H04J3/0688 ,  H04J3/1611

摘要： A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.

摘要翻译： 使用中央处理单元的总线来同步单元之间的定时信号的发送装置，从而抑制布线规模的扩大。 参考信号发生器产生参考信号。 参考信号接收器安装在作为主动或备用单元的单元上，并接收参考信号。 定时信号发生器借助于分频器/计数器来分频接收的参考信号的频率，以产生定时信号。 计数器持有分频器/计数器的计数值。 总线连接单元和中央处理单元。 计数接收器通过总线接收来自有效单元的计数器持有者的计数值。 计数更新器将分频器/计数器的计数值更新为计数接收器接收的计数值。

公开(公告)号：US20050180318A1

公开(公告)日：2005-08-18

申请号：US10869961

申请日：2004-06-18

申请人： Tomoyuki Yamamoto ,  Masahiro Shioda

发明人： Tomoyuki Yamamoto ,  Masahiro Shioda

IPC分类号： H04M3/22 ,  G01R31/02 ,  G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/00 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L49/555 ,  G01R31/023

摘要： The invention relates to a subordinate apparatus and a superordinate apparatus. The object thereof is to surely detecting an erroneous connection in a wiring between these apparatus and identifying an erroneously connected cable. A subordinate apparatus has an identifier acquiring section acquiring an identifier that is granted by a superordinate apparatus via a communication link that is formed via a first cable. When granted a new identifier via the communication link, the identifier acquiring section makes a first judgment as to whether there is an identifier granted prior to the new identifier. The identifier acquiring section nullifies the new identifier if there is an identifier granted prior to the new identifier.

摘要翻译： 本发明涉及下级装置和上级装置。 其目的是确保检测这些装置之间的布线中的错误连接并识别错误连接的电缆。 下级装置具有标识符获取部，其通过经由第一电缆形成的通信链路获取由上级装置许可的标识符。 当通过通信链路授予新的标识符时，标识符获取部分对于在新的标识符之前是否存在被许可的标识符进行第一判断。 如果在新标识符之前存在被许可的标识符，则标识符获取部分使新的标识符无效。