公开(公告)号：US20200027923A1

公开(公告)日：2020-01-23

申请号：US16299660

申请日：2019-03-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshiya MURAKAMI ,  Akihiro KAJITA ,  Masumi SAITOH

IPC: H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a memory device includes first and second electrically conductive portions, a first variable resistance portion, and a first region. A direction from the first electrically conductive portion toward the second electrically conductive portion is aligned with a first direction. The first variable resistance portion is provided between the first and second electrically conductive portions. A second direction from the first variable resistance portion toward the first region crosses the first direction. The first region includes a first layer portion, and a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction. A first distance between the first and second layer portions is longer than first or second lattice length. The first lattice length is a lattice length of the first layer portion. The second lattice length is a lattice length of the second layer portion.

公开(公告)号：US20200303641A1

公开(公告)日：2020-09-24

申请号：US16556057

申请日：2019-08-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke IKENO ,  Akihiro KAJITA ,  Atsuko SAKATA

IPC: H01L45/00 ,  H01L27/24

Abstract: According to one embodiment, a storage device includes a first conductive layer, a second conductive layer, a resistance-variable layer, between the first conductive layer and the second conductive layer, that includes germanium, antimony, and tellurium, a first layer, between the resistance-variable layer and the first conductive layer, that includes carbon, a second layer, between the resistance-variable layer and the second conductive layer, that includes carbon, a third layer, between the resistance-variable layer and the first layer, that includes at least one of tungsten nitride or tungsten carbide, and a fourth layer, between the resistance-variable layer and the second layer, that includes at least one of tungsten nitride or tungsten carbide.

公开(公告)号：US20180261624A1

公开(公告)日：2018-09-13

申请号：US15688646

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Taishi ISHIKURA ,  Atsunobu ISOBAYASHI ,  Masayuki KITAMURA ,  Akihiro KAJITA

IPC: H01L27/11582 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/00

Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.