公开(公告)号：US11145545B2

公开(公告)日：2021-10-12

申请号：US16290851

申请日：2019-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru Oda

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/092 ,  H01L27/12 ,  H01L23/535 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor substrate, a source or drain layer provided in the semiconductor substrate, a gate insulation layer provided on a surface of the semiconductor substrate, and a gate electrode that is provided on the gate insulation layer. The semiconductor device further includes a first contact that is provided on the source or drain layer, the first contact including a stacked body in which a plurality of first layers and one or more second layers are alternately stacked, and a second contact that faces at least one of a side surface and an upper surface of the first contact disposed on the source or drain layer.

公开(公告)号：US10734445B2

公开(公告)日：2020-08-04

申请号：US15910786

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru Oda ,  Akira Yotsumoto ,  Kotaro Noda

IPC: H01L29/786 ,  H01L27/24 ,  H01L23/528 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L29/06

Abstract: A storage device including a transistor portion including a transistor, a plurality of interlayer insulating films provided above the transistor portion, a plurality of first conductive layers provided respectively between the plurality of interlayer insulating films, and a second conductive layer extending through the plurality of interlayer insulating films and the plurality of first conductive layers, the second conductive layer having one end electrically connected to the transistor portion, and a part that extends beyond a portion of the transistor portion.

公开(公告)号：US10043864B2

公开(公告)日：2018-08-07

申请号：US15223632

申请日：2016-07-29

Applicant: Toshiba Memory Corporation

Inventor： Minoru Oda ,  Shinji Mori ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

公开(公告)号：US09985136B2

公开(公告)日：2018-05-29

申请号：US15260981

申请日：2016-09-09

Applicant: Toshiba Memory Corporation

Inventor： Minoru Oda ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L29/66757 ,  H01L29/7866 ,  H01L29/78696

Abstract: According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction. The third semiconductor region is provided between the first and the second semiconductor regions. The third conductor is separated from the third semiconductor region in a second direction intersecting the first direction. The third semiconductor region includes first and second partial regions. The first partial region includes a first metal element, and is amorphous. The second partial region is stacked with the first partial region in the second direction, and is polycrystalline. A first concentration of the first metal element in the first partial region is higher than a second concentration of the first metal element in the second partial region, or the second partial region does not include the first metal element.