公开(公告)号：US10833103B2

公开(公告)日：2020-11-10

申请号：US16563627

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka Sakuma ,  Hidenori Miyagawa ,  Shosuke Fujii ,  Kiwamu Sakuma ,  Fumitaka Arai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L29/51 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

公开(公告)号：US10832742B2

公开(公告)日：2020-11-10

申请号：US16549844

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes a first wire extending in a first direction from a first end to a second end, a plurality of second wires spaced from each other in the first direction and extending in a second direction intersecting the first direction, and a plurality of memory films spaced from each other along the first wire from the first end to the second end and respectively being between the first wire and a second wire of the plurality of second wires. A first memory film of the plurality is at position along the first wire that is between a position of a second memory film and the first end. A contact area between the second memory film and the first wire is greater than a contact area between the first memory film and the first wire.

公开(公告)号：US10347650B1

公开(公告)日：2019-07-09

申请号：US16058210

申请日：2018-08-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kiwamu Sakuma ,  Kensuke Ota ,  Masumi Saitoh

IPC: H01L29/76 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/786 ,  H01L29/04 ,  H01L29/423

Abstract: A semiconductor memory device includes: a substrate; a memory cell array including memory cells arranged in a first direction intersecting a surface of the substrate; an insulating layer covering the memory cell array; and a transistor provided on the insulating layer. The transistor includes: first and second semiconductor layers provided on the insulating layer; a gate electrode provided between the first and second semiconductor layers, one end in the first direction of the gate electrode being closer to the substrate than the first and second semiconductor layers; a gate insulating film provided on the one end and on side surfaces of the gate electrode; and a third semiconductor layer facing the one end and the side surfaces of the gate electrode. The third semiconductor layer includes a crystal grain larger than a shortest distance between the insulating layer and the gate insulating film.

公开(公告)号：US10043864B2

公开(公告)日：2018-08-07

申请号：US15223632

申请日：2016-07-29

Applicant: Toshiba Memory Corporation

Inventor： Minoru Oda ,  Shinji Mori ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

公开(公告)号：US09818757B2

公开(公告)日：2017-11-14

申请号：US15072722

申请日：2016-03-17

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/24 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/786 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/7869 ,  H01L29/7926

Abstract: This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.

公开(公告)号：US20200265872A1

公开(公告)日：2020-08-20

申请号：US16549844

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes a first wire extending in a first direction from a first end to a second end, a plurality of second wires spaced from each other in the first direction and extending in a second direction intersecting the first direction, and a plurality of memory films spaced from each other along the first wire from the first end to the second end and respectively being between the first wire and a second wire of the plurality of second wires. A first memory film of the plurality is at position along the first wire that is between a position of a second memory film and the first end. A contact area between the second memory film and the first wire is greater than a contact area between the first memory film and the first wire.

公开(公告)号：US10418551B2

公开(公告)日：2019-09-17

申请号：US15391039

申请日：2016-12-27

Applicant: Toshiba Memory Corporation

Inventor： Chika Tanaka ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.

公开(公告)号：US10038032B2

公开(公告)日：2018-07-31

申请号：US15062672

申请日：2016-03-07

Applicant: Toshiba Memory Corporation

Inventor： Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Toshiyuki Sasaki

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L29/66666 ,  H01L29/78642 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.

公开(公告)号：US10008509B2

公开(公告)日：2018-06-26

申请号：US15648149

申请日：2017-07-12

Applicant: Toshiba Memory Corporation

Inventor： Haruka Sakuma ,  Kiwamu Sakuma ,  Masahiro Kiyotoshi

IPC: H01L27/1157 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11578 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/1157 ,  B82Y10/00 ,  H01L27/11578 ,  H01L29/0673 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/792

Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.

公开(公告)号：US09805927B2

公开(公告)日：2017-10-31

申请号：US15134969

申请日：2016-04-21

Applicant: Toshiba Memory Corporation

Inventor： Shosuke Fujii ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L27/115 ,  H01L21/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578

CPC classification number: H01L21/02238 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7843

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.