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公开(公告)号：US5557437A
公开(公告)日：1996-09-17
申请号：US487444
申请日：1995-06-07
申请人： Toshiharu Sakai , Yoshinori Nakamura , Takashi Umegaki , Nobuo Iguchi , Miki Hagino , Hiroaki Mori , Toshikazu Ota , Akihiko Oka , Kazuo Takatsu , Nobuyuki Nemoto
发明人： Toshiharu Sakai , Yoshinori Nakamura , Takashi Umegaki , Nobuo Iguchi , Miki Hagino , Hiroaki Mori , Toshikazu Ota , Akihiko Oka , Kazuo Takatsu , Nobuyuki Nemoto
IPC分类号： H04B10/035 , H04B10/07 , H04B10/077 , H04B10/08 , H04B10/00
CPC分类号： H04B10/075 , H04B10/079
摘要： An optical terminal system having self-monitoring function is disclosed, which includes a high-level group loopback section for internally looping back a serial electric signal, a low-level group loopback section for internally looping back a parallel electric signal, a self-loop section for connecting a receiver device and a transmitter device to loop an electric signal received by the receiver device directly to the transmitter device, and a self-monitoring controller for performing a self-monitoring test on respective components of the receiver device and transmitter device by using the self-loop section and either one of the high-level group loopback section and the low-level group loopback section. The optical terminal system can selfcheck the functions thereof through self-monitoring without depending on a network.
摘要翻译： 公开了一种具有自我监测功能的光学终端系统，其包括用于内部循环串行电信号的高级组环回部分，用于内部环回并行电信号的低级组环回部分，自回路 用于连接接收机设备和发射机设备的部分，以将由接收机设备接收的电信号直接发送到发射机设备;以及自监控控制器，用于通过接收机设备和发射机设备的各个组件执行自我监测测试， 使用自环路部分和高级组环回部分和低级组环回部分之一。 光学终端系统可以通过自我监视来自行检查其功能，而不依赖于网络。
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2.发明授权Synchronous transfer mode/asynchronous transfer mode converting transmission path terminating apparatus 失效同步传输模式/异步传输模式转换传输路径终端设备
公开(公告)号：US5920563A
公开(公告)日：1999-07-06
申请号：US790216
申请日：1997-02-01
申请人： Satoshi Fukui , Toshikazu Ota , Hiroyuki Shimono , Masami Hashizume , Toshiharu Sakai , Tomoyuki Yamaguchi
发明人： Satoshi Fukui , Toshikazu Ota , Hiroyuki Shimono , Masami Hashizume , Toshiharu Sakai , Tomoyuki Yamaguchi
CPC分类号： H04Q11/0478 , H04J3/14 , H04J2203/0089 , H04L2012/5674
摘要： In a synchronous transfer mode/asynchronous transfer mode converting transmission path terminating apparatus, a receive synchronous transfer mode processing unit has an out of synchronization detecting unit for detecting out of synchronization information, and an asynchronous transfer mode cell extracting unit has an asynchronous transfer mode cell synchronizing unit for forcibly outputting a signal representing out of synchronization when receiving the out of synchronization information from the out of synchronization detecting unit, an asynchronous transfer mode cell discard judging unit for forcibly outputting a cell discard signal when receiving the out of synchronization information from the out of synchronization detecting unit, and a storage write controlling unit for forcibly inhibiting an asynchronous transfer mode cell from being written in a storage unit when receiving the out of synchronization information from the out of synchronization detecting unit, thereby always capturing accurate data (cells) to continue a process even immediately after generation of an alarm such as an SEF signal, besides transferring error information used to accurately switch a transmission path so as to prevent unnecessary switching of the transmission path.
摘要翻译： 在同步传输模式/异步传输模式转换传输路径终端设备中，接收同步传输模式处理单元具有用于检测不同步信息的异步检测单元，异步传输模式单元提取单元具有异步传输模式单元 同步单元，用于当从同步异步检测单元接收到不同步信息时，强制地输出表示不同步的信号;异步传输模式单元丢弃判断单元，用于当从所述异步传输模式单元丢弃判断单元接收到来自 不同步检测单元，以及存储写入控制单元，用于当从异步检测单元接收到不同步信息时强制禁止异步传输模式单元写入存储单元，从而总是捕获 环形精确数据（单元），甚至在产生诸如SEF信号的警报之后立即继续处理，除了传输用于精确地切换传输路径的错误信息，以防止传输路径的不必要的切换。
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公开(公告)号：US09166739B2
公开(公告)日：2015-10-20
申请号：US13488741
申请日：2012-06-05
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/6561
摘要： An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.
摘要翻译： 纠错处理电路包括：分割电路，将输入数据分割为预定数据长度的多个片段; 多个并行设置的运算电路，分别对由分割电路分割的多条数据进行纠错运算; 多路复用电路，对由多个运算电路进行了运算的多条数据进行复用; 以及输出由多路复用电路复用的数据的输出电路。
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公开(公告)号：US5062069A
公开(公告)日：1991-10-29
申请号：US407376
申请日：1989-09-14
申请人： Yasuo Takasu , Toshiharu Sakai , Seiichi Shindo , Takumi Kanazawa
发明人： Yasuo Takasu , Toshiharu Sakai , Seiichi Shindo , Takumi Kanazawa
摘要： Test equipment for a Multi Channel Access (MCA) wireless apparatus includes a Read/Write memory section which operationally replaces an ID.ROM of the apparatus for the purpose of the testing. A personal computer writes area, channel, system, tone group and user code data into the memory section which is read by the operating section in order to configure its channel setting. A measuring device receives code data for a channel setting at which operation is to be checked, sends a corresponding channel designating signal to the wireless apparatus, receives a response signal from the wireless, and forms and sends to the personal computer a result signal indicative of whether the response signal is accepted or rejected. The personal computer operates to send the code data to the measuring device under program control in response to keyboard operation by the user.
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5.发明申请公开(公告)号：US20120331364A1
公开(公告)日：2012-12-27
申请号：US13488741
申请日：2012-06-05
IPC分类号： G06F11/07
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/6561
摘要： An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.
摘要翻译： 纠错处理电路包括：分割电路，将输入数据分割为预定数据长度的多个片段; 多个并行设置的运算电路，分别对由分割电路分割的多条数据进行纠错运算; 多路复用电路，对由多个运算电路进行了运算的多条数据进行复用; 以及输出由多路复用电路复用的数据的输出电路。
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