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    Cover of lighting unit for vehicle
    1.
    发明授权
    Cover of lighting unit for vehicle 失效
    汽车照明单元盖

    公开(公告)号：US07303807B2

    公开(公告)日：2007-12-04

    申请号：US10825682

    申请日：2004-04-16

    申请人： Toshimasa Ikeda ,  Masami Nakajima

    发明人： Toshimasa Ikeda ,  Masami Nakajima

    IPC分类号： B32B3/00 ,  F21V7/00 ,  F21V5/00

    CPC分类号： B32B27/08 ,  B29C45/16 ,  B29C2045/1682 ,  B29K2995/0025 ,  B29K2995/0026 ,  B29L2011/0016 ,  B29L2031/30 ,  B29L2031/747 ,  B32B3/02 ,  B32B2307/402 ,  F21S43/255 ,  F21S43/26 ,  F21V3/04 ,  Y10T428/24479 ,  Y10T428/24562 ,  Y10T428/24612

    摘要： A lighting unit cover including a deep color (first) resin layer subject to preblanking is laminated and molded in a predetermined position on a backside of a light color (second) resin layer on a surface side subject to postblanking. The second layer protrudes toward the first layer side and a boundary surface between the first and second layers and is offset by a distance toward the first layer side in a laminated portion. The first layer contacts the melted second resin and is subject to postblanking so that a part thereof is molten and drawn by its flow. A step portion in a cavity corresponding to a protruded portion of the second layer toward the first layer side blocks the flow of the molten first resin into the second layer. The first resin is not mixed into the first layer, resulting in excellent appearance and a large light emitting area.

    摘要翻译： 包含经受预浸的深色（第一）树脂层的照明单元盖层叠并模制在预沉积后的表面侧上的浅色（第二）树脂层的背面上的预定位置。 第二层向第一层侧突出，在第一层和第二层之间的边界面突出，并且在层叠部分中偏移到第一层侧的距离。 第一层与熔融的第二树脂接触并进行后冲压，使其一部分熔融并通过其流动拉伸。 对应于第二层朝向第一层侧的突出部分的空腔中的阶梯部分阻止熔融的第一树脂流入第二层。 第一树脂不混入第一层，外观优异，发光面积大。

    Cover of lighting unit for vehicle
    4.
    发明申请
    Cover of lighting unit for vehicle 失效
    汽车照明单元盖

    公开(公告)号：US20050003159A1

    公开(公告)日：2005-01-06

    申请号：US10825682

    申请日：2004-04-16

    申请人： Toshimasa Ikeda ,  Masami Nakajima

    发明人： Toshimasa Ikeda ,  Masami Nakajima

    IPC分类号： B60Q1/04 ,  B29C45/16 ,  B32B3/02 ,  B32B27/08 ,  F21S8/10 ,  F21V3/04 ,  F21V5/00 ,  F21W101/12 ,  F21W101/14 ,  B32B3/00

    CPC分类号： B32B27/08 ,  B29C45/16 ,  B29C2045/1682 ,  B29K2995/0025 ,  B29K2995/0026 ,  B29L2011/0016 ,  B29L2031/30 ,  B29L2031/747 ,  B32B3/02 ,  B32B2307/402 ,  F21S43/255 ,  F21S43/26 ,  F21V3/04 ,  Y10T428/24479 ,  Y10T428/24562 ,  Y10T428/24612

    摘要： A lighting unit cover including a deep color (first) resin layer subject to preblanking is laminated and molded in a predetermined position on a backside of a light color (second) resin layer on a surface side subject to postblanking. The second layer protrudes toward the first layer side and a boundary surface between the first and second layers and is offset by a distance toward the first layer side in a laminated portion. The first layer contacts the melted second resin and is subject to postblanking so that a part thereof is molten and drawn by its flow. A step portion in a cavity corresponding to a protruded portion of the second layer toward the first layer side blocks the flow of the molten first resin into the second layer. The first resin is not mixed into the first layer, resulting in excellent appearance and a large light emitting area.

    摘要翻译： 包含经受预浸的深色（第一）树脂层的照明单元盖层叠并模制在预沉积后的表面侧上的浅色（第二）树脂层的背面上的预定位置。 第二层向第一层侧突出，在第一层和第二层之间的边界面突出，并且在层叠部分中偏移到第一层侧的距离。 第一层与熔融的第二树脂接触并进行后冲压，使其一部分熔融并通过其流动拉伸。 对应于第二层朝向第一层侧的突出部分的空腔中的阶梯部分阻止熔融的第一树脂流入第二层。 第一树脂不混入第一层，外观优异，发光面积大。

    Semiconductor memory device with built-in self test circuit operating at high rate
    5.
    发明授权
    Semiconductor memory device with built-in self test circuit operating at high rate 有权
    具有内置自检电路的半导体存储器件以高速率工作

    公开(公告)号：US06993696B1

    公开(公告)日：2006-01-31

    申请号：US09712246

    申请日：2000-11-15

    申请人： Tetsushi Tanizaki ,  Kazushi Sugiura ,  Masami Nakajima

    发明人： Tetsushi Tanizaki ,  Kazushi Sugiura ,  Masami Nakajima

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G11C29/36 ,  G11C29/16 ,  G11C2029/3602

    摘要： A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

    摘要翻译： 具有内置自检电路的半导体存储器件包括半导体衬底，形成在半导体衬底上的存储单元阵列，设置在半导体衬底上用于接收外部施加数据的输入缓冲器，耦合到存储单元阵列的测试电路 以及半导体衬底上的输入缓冲器，用于存储通过输入缓冲器接收的程序，以根据所存储的程序生成存储单元阵列的测试数据，以执行存储单元阵列的测试，以及选择性地应用于存储器 根据测试操作和正常操作，从测试电路应用的单元阵列测试数据和从输入缓冲器施加的数据。

    Synchronous counter
    6.
    发明授权
    Synchronous counter 失效
    同步计数器

    公开(公告)号：US06535569B2

    公开(公告)日：2003-03-18

    申请号：US09756129

    申请日：2001-01-09

    申请人： Masami Nakajima ,  Hiroyuki Kondo

    发明人： Masami Nakajima ,  Hiroyuki Kondo

    IPC分类号： H03K2354

    CPC分类号： H03K23/54

    摘要： A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flops and the input of another is one stage of a 2-input EXOR gate even in a critical path thereby shortening the critical path.

    摘要翻译： 同步计数器包括至少三个或更多个具有链结构的触发器和至少两个或更多个插入链结构中的2输入EXOR门。 插入在触发器中的一个的输出和另一个的输入之间的门的级数是即使在关键路径中的2-输入EXOR门的一个阶段，从而缩短了关键路径。

    Semiconductor integrated circuit having built-in self-test circuit
    7.
    发明授权
    Semiconductor integrated circuit having built-in self-test circuit 失效
    具有内置自检电路的半导体集成电路

    公开(公告)号：US06335645B1

    公开(公告)日：2002-01-01

    申请号：US09593079

    申请日：2000-06-13

    申请人： Yukikazu Matsuo ,  Masami Nakajima ,  Tetsushi Tanizaki

    发明人： Yukikazu Matsuo ,  Masami Nakajima ,  Tetsushi Tanizaki

    IPC分类号： H03L700

    CPC分类号： G01R31/3016 ,  H03L7/00

    摘要： When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes. Therefore, because the for-synchronization-circuit enabling signal is not received from the outsides but is produced, a circuit area of a semiconductor integrated circuit can be efficiently used.

    摘要翻译： 当异步内部时钟使能信号与外部时钟信号异步的电平在外部时钟信号的电平变化之后或之前上升时，与外部时钟信号同步的同步电路使能信号在 条件是在外部时钟信号的两个时钟的外部时钟信号的电平变化晚的同时电路使能信号的电平上升的条件下，控制信号产生电路。 因此，获得从外部时钟信号的电平变化到同步电路使能信号的电平变化的复位时间段。 根据外部时钟信号和异步内部时钟使能信号，在复位时间段中复位同步电路，并且在复位时间允许信号之后，从同步电路使能信号在同步电路中产生测试信号， 期间通行证。 因此，由于没有从外部接收到同步电路使能信号，而是被产生，因此可以有效地使用半导体集成电路的电路区域。

    Conveying Apparatus and Conveyed Object Inspection Apparatus
    8.
    发明申请
    Conveying Apparatus and Conveyed Object Inspection Apparatus 有权
    输送装置和输送对象检查装置

    公开(公告)号：US20090139832A1

    公开(公告)日：2009-06-04

    申请号：US12302393

    申请日：2007-05-25

    申请人： Takemitu Sato ,  Satoshi Hasegawa ,  Masami Nakajima ,  Yasushi Toyama ,  Haruo Miyata

    发明人： Takemitu Sato ,  Satoshi Hasegawa ,  Masami Nakajima ,  Yasushi Toyama ,  Haruo Miyata

    IPC分类号： B65G33/06 ,  B65G43/08

    CPC分类号： B65G33/06 ,  B65G33/26 ,  B65G33/265

    摘要： A conveying apparatus and a conveyed object inspection apparatus which can perform accurate, damage free image inspection. One conveying roller has a conveying surface formed in a spiral manner on an outer periphery surface thereof. The conveying surface is slanted with respect to the central axis narrowing toward other end side so as to convey a conveyed object while holding it between the conveying surface and other conveying roller. The other conveying roller has a tilt surface provided in a spiral manner on an outer periphery surface thereof. The tilt surface is slanted with respect to the central axis narrowing toward one end side. A feeding means can feed the conveyed object inbetween the conveying rollers. An inspection section has an image acquisition means capable of acquiring an image of an entire outer surface of the conveyed object, and an abnormality detecting means capable of detecting abnormality of the conveyed object based on the image A removing means can then remove an abnormal object.

    摘要翻译： 可以进行精确，无损图像检查的输送装置和输送对象检查装置。 一个输送辊具有在其外周面上以螺旋方式形成的输送表面。 输送表面相对于朝向另一端侧变窄的中心轴线倾斜，以便在将其保持在输送表面和其它输送辊之间时输送被输送物体。 另一个输送辊具有在其外周表面上以螺旋方式设置的倾斜表面。 倾斜表面相对于朝向一端侧变窄的中心轴倾斜。 进给装置可以将输送的物体送入传送辊之间。 检查部分具有能够获取被输送物体的整个外表面的图像的图像获取装置，以及能够基于图像检测被传送物体的异常的异常检测装置。 然后，移除装置可以移除异常物体。

    Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator
    9.
    发明授权
    Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator 有权
    处理器，用于根据指令状态指示器执行包含单个操作或打包多个操作的指令

    公开(公告)号：US07473293B2

    公开(公告)日：2009-01-06

    申请号：US11520616

    申请日：2006-09-14

    申请人： Masami Nakajima

    发明人： Masami Nakajima

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3853 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/3822

    摘要： A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in accordance with the decoding result of the instruction decoder. Therefore, the number of instructions that can be executed in parallel per cycle may be increased while at the same time the capacity of the instruction memory is reduced.

    摘要翻译： 转换表将从指令存储器取出的指令码中包含的压缩指令（预转换代码）转换为多个指令代码（转换代码）。 指令解码器对由转换表转换的多个指令代码进行解码。 多个ALU根据指令解码器的解码结果执行操作。 因此，可以增加每个周期可以并行执行的指令的数量，同时减少指令存储器的容量。

    Processor enabling input/output of data during execution of operation
    10.
    发明授权
    Processor enabling input/output of data during execution of operation 失效
    处理器在执行操作期间能够输入/输出数据

    公开(公告)号：US07953938B2

    公开(公告)日：2011-05-31

    申请号：US11907049

    申请日：2007-10-09

    申请人： Masami Nakajima

    发明人： Masami Nakajima

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1605 ,  G06F13/4022

    摘要： When free bank information representing that a bank is not used by a PE and outputted from a PE controller coincides with used bank information representing that a bank is used for data transfer and outputted from a bus controller, a memory controller controls LM-banks 0 to 3 and a switching network so as to enable all communications. Therefore, data reading and data writing by the PE is performed in parallel with the data transfer with the outside, so that processing time of the PE can be reduced.

    摘要翻译： 代表PE不使用银行并从PE控制器输出的空闲银行信息与表示银行用于数据传输并从总线控制器输出的所使用的银行信息一致时，存储器控制器将LM库0至 3和交换网络，以便能够进行所有通信。 因此，与外部的数据传送并行地执行PE的数据读取和数据写入，从而可以减少PE的处理时间。