公开(公告)号：US5526509A

公开(公告)日：1996-06-11

申请号：US386757

申请日：1995-02-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

公开(公告)号：US5392416A

公开(公告)日：1995-02-21

申请号：US103791

申请日：1993-08-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

摘要翻译： 用于多处理器系统的集成电路结构的处理装置包括基于虚拟存储方案操作的执行单元和具有来自执行单元的逻辑地址指定的条目的高速缓冲存储器。 为了控制高速缓冲存储器，提供包含与高速缓冲存储器相同的逻辑地址指定的条目并存储用于高速缓存存储器的对应条目的控制信息的第一地址阵列与具有由物理地址指定的条目的第二地址阵列相关联， 将用于翻译物理地址的翻译信息存储到条目的逻辑地址。 当响应于外部提供的高速缓冲存储器无效请求输入要执行无效的物理地址时，通过使用物理地址对第二地址阵列进行访问，以从第二地址阵列获得翻译信息，从而生成 一个无效的逻辑地址。 通过使用所生成的逻辑地址对控制信息进行无效处理来访问第一地址阵列。

公开(公告)号：US5257361A

公开(公告)日：1993-10-26

申请号：US603620

申请日：1990-10-26

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

摘要翻译： 用于多处理器系统的集成电路结构的处理装置包括基于虚拟存储方案操作的执行单元和具有来自执行单元的逻辑地址指定的条目的高速缓冲存储器。 为了控制高速缓冲存储器，提供包含与高速缓冲存储器相同的逻辑地址指定的条目并存储用于高速缓存存储器的对应条目的控制信息的第一地址阵列与具有由物理地址指定的条目的第二地址阵列相关联， 将用于翻译物理地址的翻译信息存储到条目的逻辑地址。 当响应于外部提供的高速缓冲存储器无效请求输入要执行无效的物理地址时，通过使用物理地址对第二地址阵列进行访问，以从第二地址阵列获得翻译信息，从而生成 一个无效的逻辑地址。 通过使用所生成的逻辑地址对控制信息进行无效处理来访问第一地址阵列。

公开(公告)号：US5784630A

公开(公告)日：1998-07-21

申请号：US367928

申请日：1995-01-03

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

公开(公告)号：US5968160A

公开(公告)日：1999-10-19

申请号：US923632

申请日：1997-09-04

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

公开(公告)号：US5544340A

公开(公告)日：1996-08-06

申请号：US362755

申请日：1994-12-22

申请人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

发明人： Toshio Doi ,  Takehisa Hayashi ,  Kenichi Ishibashi ,  Takeshi Takemoto

IPC分类号： G06F12/08

CPC分类号： G06F12/0886

摘要： A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

摘要翻译： 一种控制设置在CPU和主存储器之间的高速缓冲存储器的方法，其中将要写入高速缓冲存储器的数据和地址对存储在缓冲存储器中。 处理从缓冲存储器读取的多对数据和地址，以比较其地址字段。 基于比较的结果，确定了将数据写入高速缓冲存储器中的写入控制，其被细分为多个存储体。 结果，将多对数据和地址写入高速缓冲存储器的多个组，各对的地址彼此不同。 通过上述规定，可以对高速缓冲存储器的每一组独立地进行写入操作，从而提高写入吞吐量。

公开(公告)号：US08018203B2

公开(公告)日：2011-09-13

申请号：US12375956

申请日：2007-08-20

申请人： Yuji Nishi ,  Takeshi Takemoto

发明人： Yuji Nishi ,  Takeshi Takemoto

IPC分类号： H02J7/00

CPC分类号： B60W20/13 ,  B60K6/365 ,  B60K6/445 ,  B60L3/0046 ,  B60L3/0053 ,  B60L11/1874 ,  B60L11/1887 ,  B60L11/1892 ,  B60L2240/423 ,  B60L2260/56 ,  B60W10/08 ,  B60W10/26 ,  B60W10/28 ,  B60W20/00 ,  B60W30/18127 ,  B60W2510/244 ,  B60W2520/10 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2710/083 ,  B60W2710/244 ,  H01M10/0525 ,  H01M10/44 ,  H01M10/484 ,  H02J7/0075 ,  Y02E60/122 ,  Y02T10/56 ,  Y02T10/6239 ,  Y02T10/642 ,  Y02T10/7011 ,  Y02T10/705 ,  Y02T90/34

摘要： A battery model unit includes an electrode reaction model unit based on the Butler_Volmer equation, an electrolyte lithium concentration distribution model unit analyzing a lithium ion concentration distribution in an electrolyte solution by a diffusion equation, an active material lithium concentration distribution model unit analyzing an ion concentration distribution in a solid state of an active material by a diffusion equation, a current/potential distribution model unit for obtaining a potential distribution according to the charge conservation law, a thermal diffusion model unit and a boundary condition setting unit. The boundary condition setting unit (66) sets a boundary condition at an electrode interface such that a reacting weight at the electrode interface is not determined by a difference in material concentration between positions but a deviation from an electrochemically balanced state causes a change with time in lithium concentration at the interface and thus a (time-based) drive power for material transportation. Thereby, an appropriate charge/discharge control can be performed based on the battery model having the appropriately set battery condition.

摘要翻译： 电池模型单元包括基于Butler_Volmer方程的电极反应模型单元，通过扩散方程分析电解质溶液中的锂离子浓度分布的电解质锂浓度分布模型单元，分析离子浓度的活性物质锂浓度分布模型单元 通过扩散方程分布在活性物质的固体状态，用于根据电荷守恒定律获得电位分布的电流/电位分布模型单元，热扩散模型单元和边界条件设置单元。 边界条件设定部（66）将电极界面处的边界条件设定为使得电极界面处的反应重量不由位置之间的材料浓度的差异决定，而与电化学平衡状态的偏离导致随时间的变化 界面处的锂浓度，因此用于材料输送的（基于时间）驱动功率。 因此，可以基于具有适当设定的电池状态的电池模型来进行适当的充放电控制。

公开(公告)号：US07912412B2

公开(公告)日：2011-03-22

申请号：US12073501

申请日：2008-03-06

申请人： Takashi Fujita ,  Shin Kayahara ,  Takeshi Takemoto ,  Hiromitsu Takagaki ,  Takashi Seto ,  Hirohmi Tamura

发明人： Takashi Fujita ,  Shin Kayahara ,  Takeshi Takemoto ,  Hiromitsu Takagaki ,  Takashi Seto ,  Hirohmi Tamura

IPC分类号： G03G15/16

CPC分类号： G03G15/161 ,  G03G15/2064 ,  G03G2215/0129 ,  G03G2215/1685 ,  G03G2215/2074

摘要： A transfer-fixing device transfers and fixes a toner image onto a transfer-fixing surface of a recording medium, and includes a transfer-fixing member, a pressing member, a heating member, and a temperature equalization member. The transfer-fixing member carries the toner image. The pressing member pressingly contacts the transfer-fixing member to form a nip between the pressing member and the transfer-fixing member through which the recording medium passes. The heating member heats the transfer-fixing surface of the recording medium conveyed toward the nip so that the recording medium reaches the nip before a temperature of a back surface opposite the transfer-fixing surface of the recording medium increases. The temperature equalization member equalizes temperature distribution on a surface of the transfer-fixing member in a width direction of the transfer-fixing member perpendicular to a conveyance direction of the recording medium, after the surface of the transfer-fixing member passes the nip.

摘要翻译： 转印固定装置将调色剂图像转印并固定到记录介质的转印固定表面上，并且包括转印固定构件，按压构件，加热构件和温度均衡构件。 转印固定构件承载调色剂图像。 按压构件按压接触转印固定构件，以在按压构件和记录介质通过的转印固定构件之间形成辊隙。 加热构件加热朝向辊隙传送的记录介质的转印固定表面，使得记录介质在与记录介质的转印固定表面相对的背面的温度增加之前到达辊隙。 所述温度均衡部件在所述转印固定部件的表面经过所述辊隙之后，使所述转印固定部件的表面上的转印固定部件的表面上的温度分布与所述记录介质的输送方向垂直的方向相等。

公开(公告)号：US20100153038A1

公开(公告)日：2010-06-17

申请号：US12449390

申请日：2008-03-13

申请人： Shuji Tomura ,  Takaji Umeno ,  Yasushi Amano ,  Yuji Nishi ,  Takeshi Takemoto ,  Nobuyasu Haga ,  Tetsuya Fuchimoto

发明人： Shuji Tomura ,  Takaji Umeno ,  Yasushi Amano ,  Yuji Nishi ,  Takeshi Takemoto ,  Nobuyasu Haga ,  Tetsuya Fuchimoto

IPC分类号： G01R31/36 ,  G06F19/00

CPC分类号： G01R31/3675 ,  G01R31/3624 ,  G01R31/3662 ,  G01R31/3679

摘要： A battery state estimating unit (110) estimates an internal state of a secondary battery according to a battery model equation in every arithmetic cycle, and calculates an SOC based on a result of the estimation. A parameter characteristic map (120) stores a characteristic map based on a result of actual measurement performed in an initial state (in a new state) on a parameter diffusion coefficient (Ds) and a DC resistance (Ra) in the battery model equation. The parameter change rate estimating unit (130) estimates a DC resistance change rate (gr) represented by a ratio of a present DC resistance (Rc) with respect to a new-state parameter value (Ran) by parameter identification based on the battery model equation, using battery data (Tb, Vb and Ib) measured by sensors as well as the new-state parameter value (Ran) of the DC resistance corresponding to the p resent battery state and read from the parameter characteristic map (120).

摘要翻译： 电池状态估计单元（110）根据每个运算周期中的电池模型方程来估计二次电池的内部状态，并且基于估计结果来计算SOC。 参数特征图（120）基于在初始状态（新状态下）对电池模型方程式中的参数扩散系数（Ds）和直流电阻（Ra）进行的实际测量的结果来存储特性图。 参数变化率估计单元（130）基于电池模型通过参数识别来估计由当前直流电阻（Rc）相对于新状态参数值（Ran）的比率所表示的直流电阻变化率（gr） 方程式，使用由传感器测量的电池数据（Tb，Vb和Ib）以及与参数电池状态对应的直流电阻的新状态参数值（Ran），并从参数特性图（120）读取。

公开(公告)号：US20070212126A1

公开(公告)日：2007-09-13

申请号：US11681739

申请日：2007-03-02

申请人： Takashi Seto ,  Takeshi Takemoto ,  Takashi Fujita ,  Katsuaki Miyawaki ,  Hiromitsu Takagaki ,  Shin Kayahara ,  Atsushi Nakafuji ,  Hiromi Tamura ,  Kazumi Suzuki

发明人： Takashi Seto ,  Takeshi Takemoto ,  Takashi Fujita ,  Katsuaki Miyawaki ,  Hiromitsu Takagaki ,  Shin Kayahara ,  Atsushi Nakafuji ,  Hiromi Tamura ,  Kazumi Suzuki

IPC分类号： G03G15/01

CPC分类号： G03G15/167 ,  G03G2215/0119 ,  G03G2215/1695

摘要： A transfer unit for use in an image forming apparatus includes a transfer belt, and a counter member. The transfer belt, having a given circumferential length, receives an un-fixed image, formed of an image developer, from an image carrier at a first nip, which is defined between the transfer belt and the image carrier. The counter member faces the transfer belt to form a second nip with the transfer belt. The un-fixed image is transferred from the transfer belt to a recording medium passing through the second nip. A slack portion is generated in the transfer belt, when a front edge of the recording medium passes through the second nip. The slack portion of the transfer belt being generated in a first portion of the transfer belt returning from the second nip to the first nip.

摘要翻译： 用于图像形成装置的转印单元包括转印带和计数器构件。 具有给定圆周长度的转印带在由转印带和图像载体之间限定的第一辊隙处从图像载体接收由图像显影剂形成的未固定图像。 相对构件面向转印带以与转印带形成第二辊隙。 未固定的图像从转印带传送到通过第二辊隙的记录介质。 当记录介质的前边缘通过第二压区时，在转印带中产生松弛部分。 转印带的松弛部分在转印带的第一部分中从第二辊隙返回到第一辊隙。