公开(公告)号：US20090115388A1

公开(公告)日：2009-05-07

申请号：US12288094

申请日：2008-10-16

申请人： Masato Miyazaki ,  Toshio Maejima

发明人： Masato Miyazaki ,  Toshio Maejima

IPC分类号： G05F1/00

CPC分类号： H02M3/158

摘要： A DC/DC converter is constituted of a switching element (e.g., a MOS transistor), an LC low-pass filter constituted of an inductor and a capacitor, and a control circuit for controlling the on/off timing of the switching element such that the output voltage is set to a predetermined voltage value. A series circuit (serving as a snubber circuit) constituted of a resistor and a switch is further connected in parallel with the inductor. The control circuit closes the switch so that the resistor is connected in parallel with the inductor in a resonance mode of the LC low-pass filter. Thus, it is possible to dissipate energy accumulated in the inductor in a short time without using a relatively large circuit scale, thus avoiding the occurrence of ringing.

摘要翻译： DC / DC转换器由开关元件（例如，MOS晶体管），由电感器和电容器构成的LC低通滤波器和用于控制开关元件的接通/断开定时的控制电路构成，使得 输出电压被设定为预定的电压值。 由电阻器和开关构成的串联电路（用作缓冲电路）还与电感器并联连接。 控制电路关闭开关，使得电阻器以LC低通滤波器的谐振模式与电感器并联连接。 因此，可以在短时间内消耗积聚在电感器中的能量，而不用相对较大的电路规模，从而避免发生振铃。

公开(公告)号：US20080150635A1

公开(公告)日：2008-06-26

申请号：US12004373

申请日：2007-12-20

申请人： Toshio Maejima

发明人： Toshio Maejima

IPC分类号： H03F3/217

CPC分类号： H03F3/2175

摘要： A PWM modulator adds first and second input signals to each other, and performs PWM modulation processing for outputting a PWM-modulated pulse whose pulse width is modulated according to a result of addition. A shift register delays a bit stream acquired from a ΔΣ modulator, thereby generating two bit streams having a time difference which is one-half a period of PWM modulation processing, and the bit streams are supplied at first and second input signals to the PWM modulator.

摘要翻译： PWM调制器将第一和第二输入信号彼此相加，并且执行PWM调制处理，用于输出根据加法结果来调制脉冲宽度的PWM调制脉冲。 移位寄存器延迟从DeltaSigma调制器获取的比特流，从而产生具有PWM调制处理周期的一半的时间差的两个比特流，并且将比特流以第一和第二输入信号提供给PWM调制器 。

公开(公告)号：US20050162223A1

公开(公告)日：2005-07-28

申请号：US10967807

申请日：2004-10-18

申请人： Toshio Maejima

发明人： Toshio Maejima

IPC分类号： H03F3/217 ,  H03F3/38

CPC分类号： H03F3/2171

摘要： A class-D amplifier for pulse-width-modulating an analog input signal to output a pulse-width-modulated signal, includes: a differentiating circuit for differentiating the pulse-width-modulated signal of the class-D amplifier; and a negative feedback circuit for feeding back the differentiated signal of the differentiating circuit to an input side of the class-D amplifier in a negative feedback manner.

摘要翻译： 一种用于对模拟输入信号进行脉宽调制以输出脉宽调制信号的D类放大器，包括：用于区分D类放大器的脉宽调制信号的微分电路; 以及负反馈电路，用于以负反馈的方式将差分电路的微分信号反馈到D类放大器的输入侧。

公开(公告)号：US06788792B1

公开(公告)日：2004-09-07

申请号：US09339202

申请日：1999-06-24

申请人： Toshio Maejima ,  Masao Noro

发明人： Toshio Maejima ,  Masao Noro

IPC分类号： H03G700

CPC分类号： H03G3/3026 ,  H03K7/08

摘要： An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics. A full-wave rectifier, applicable to the amplitude adjustment device, is mainly configured by an inversion amplifier, an amplifier and an output section. Herein, the inversion amplifier amplifies an input signal with a gain of “−1”, while the amplifier amplifies it with a gain of “1”. Outputs of the amplifiers differ from each other in phases by 180°. The output section produces a full-wave rectified signal based on the outputs of the amplifiers. Incidentally, all of the amplifiers and output section are configured using field-effect transistors without using diodes being externally connected. Hence, it is possible to manufacture the full-wave rectifier in a form of an IC in accordance with the MOS process with ease.

公开(公告)号：US06696877B2

公开(公告)日：2004-02-24

申请号：US10137573

申请日：2002-05-02

申请人： Toshio Maejima ,  Akihiko Toda

发明人： Toshio Maejima ,  Akihiko Toda

IPC分类号： H03L500

CPC分类号： H03F3/45475 ,  H03F1/30

摘要： Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value R0 having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount. If the amplitude center level of the output signal from the level shift circuit is represented by Vc, the level shift amount &Dgr;V can be expressed as &Dgr;V=Vc−Vref=(R1/R0)Vref With such arrangements, the level shift circuit can operate appropriately using only one reference voltage, without requiring any external capacitor.

摘要翻译： 电平移位电路包括运算放大器和输入电阻器，其一端连接到放大器电路的输出端子，另一端连接到运算放大器的反相输入端子。 电平移位电路还包括电阻值R0的电平移动电阻，其一端连接到运算放大器的反相输入端，另一端连接到地，以及电阻值R1的反馈电阻。 参考电压Vref施加到运算放大器的非反相输入端。 电平移位电路的输出信号表示放大器电路的输出已经在电平上移动预定量。 如果来自电平移位电路的输出信号的幅度中心电平由Vc表示，则电平偏移量DeltaV可以表示为这样的结构，电平移位电路可以仅使用一个参考电压适当地进行操作，而不需要任何外部电容器。

公开(公告)号：US08054129B2

公开(公告)日：2011-11-08

申请号：US12317613

申请日：2008-12-23

申请人： Toshio Maejima

发明人： Toshio Maejima

IPC分类号： H03F21/00

CPC分类号： H03F3/217 ,  H03F2200/66

摘要： A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

摘要翻译： D类放大器包括：放大器，其基于输入信号产生用于驱动负载的数字信号; 衰减器，其根据衰减命令信号衰减输入信号; 以及剪辑防止控制器，当数字信号进入剪辑状态或接近剪辑状态时，输出衰减命令信号来间断地衰减输入信号。

公开(公告)号：US20090115514A1

公开(公告)日：2009-05-07

申请号：US12317613

申请日：2008-12-23

申请人： Toshio Maejima ,  Masayuki Iwamatsu

发明人： Toshio Maejima ,  Masayuki Iwamatsu

IPC分类号： H03F3/217

CPC分类号： H03F3/217 ,  H03F2200/66

摘要： A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

公开(公告)号：US07482870B2

公开(公告)日：2009-01-27

申请号：US11541999

申请日：2006-09-28

申请人： Toshio Maejima ,  Masayuki Iwamatsu

发明人： Toshio Maejima ,  Masayuki Iwamatsu

IPC分类号： H03F21/00

CPC分类号： H03F3/217 ,  H03F2200/66

摘要： A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

摘要翻译： D类放大器包括：放大器，其基于输入信号产生用于驱动负载的数字信号; 衰减器，其根据衰减命令信号衰减输入信号; 以及剪辑防止控制器，当数字信号进入剪辑状态或接近剪辑状态时，输出衰减命令信号来间断地衰减输入信号。

公开(公告)号：US6061279A

公开(公告)日：2000-05-09

申请号：US263938

申请日：1999-03-08

申请人： Akihiro Toda ,  Masao Noro ,  Toshio Maejima

发明人： Akihiro Toda ,  Masao Noro ,  Toshio Maejima

IPC分类号： G11C27/02 ,  H03H11/26 ,  H03H19/00 ,  G11C7/00

CPC分类号： G11C27/026 ,  G11C27/024

摘要： A delay circuit is provided, which is capable of eliminating the influence of noise of low frequency as disturbance. A plurality of memory cells including a plurality of capacitors store an analog signal as an input signal by storing charge of the input signal in the capacitors. A first inverting device inverts the input signal to generate an inverted signal. A control circuit generates and delivers control signals to the memory cells to select the input signal and the inverted signal alternately and sequentially write the selected signals into the memory cells in a predetermined writing sequence. The control circuit further generates and delivers to the memory cells to sequentially read out the input signal and the inverted signal from the memory cells in a sequence corresponding to the predetermined writing sequence. A second inverting device inverts the read-out inverted signal. An output signal is synthesized from the read-out input signal and an output signal of the second inverting device.

摘要翻译： 提供了一种能够消除低频噪声对干扰的影响的延迟电路。 包括多个电容器的多个存储单元通过将输入信号的电荷存储在电容器中来存储模拟信号作为输入信号。 第一反相装置反相输入信号以产生反相信号。 控制电路产生并传送控制信号到存储器单元，以选择输入信号和反相信号交替地并按预定的写入顺序将所选择的信号写入存储单元。 控制电路进一步产生并传送到存储器单元，以与预定写入序列相对应的顺序从存储器单元顺序读出输入信号和反相信号。 第二反相装置反转读出的反相信号。 从读出输入信号和第二反相器的输出信号合成输出信号。

公开(公告)号：US6018262A

公开(公告)日：2000-01-25

申请号：US67046

申请日：1998-04-27

申请人： Masao Noro ,  Yusuke Yamamoto ,  Toshio Maejima

发明人： Masao Noro ,  Yusuke Yamamoto ,  Toshio Maejima

IPC分类号： H03M3/02 ,  H03K5/08

CPC分类号： H03M3/444 ,  H03M3/43

摘要： An analog-digital converter includes a .DELTA..SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA..SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA..SIGMA. modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.

摘要翻译： 模拟数字转换器包括串联连接的DELTA SIGMA调制器，数字滤波器，高通滤波器和乘法器。 模拟输入通过DELTA SIGMA调制器转换成串行位串，为其设置增益'1 / A'。 数字滤波器从串行比特串中提取与模拟输入相对应的低频分量，因此低频分量转换为并行位数字数据。 高通滤波器从数字滤波器的输出中去除直流偏移分量; 然后，通过乘法器将其输出乘以缩放增益“A”，从而产生数字输出。 DELTA SIGMA调制器包括串联连接的至少三个开关电容积分器和一位量化器以及单采样延迟电路。 由一位量化器产生的一位输出由单采样延迟电路延迟，其中输出被传送到每个开关电容积分器。 每个开关电容积分器使用由CMOS运算放大器和至少一个幅度限制电路配置的CMOS差分放大器来配置。 限幅电路由两个PMOS晶体管和两个以二极管连接方式并联连接的NMOS晶体管构成; 并且该电路被提供以通过稳定其工作点来限制CMOS差分放大器的输出的幅度。