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    Output circuit
    1.
    发明授权
    Output circuit 失效
    输出电路

    公开(公告)号：US4408094A

    公开(公告)日：1983-10-04

    申请号：US197431

    申请日：1980-10-16

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: H02M7/537 ,  G10L19/00 ,  H04R3/00 ,  H03K13/02

    CPC classification number: G10L19/00

    Abstract: An improved output circuit for driving a loudspeaker with a single-polarity current source is disclosed. The output circuit comprises a digital to analog converter including a series circuit of a variable register and a field effect transistor for generating a variable bias potential, a plurality of current source transistors and a plurality of transfer field transistors each for selectively applying the variable bias potential to a gate of an associated current source transistor in accordance with a digital signal; a loudspeaker; and two pairs of switching transistors for alternately supplying the loudspeaker with different polarities of an output current of the digital to analog converter.

    Abstract translation: 公开了用于驱动具有单极性电流源的扬声器的改进的输出电路。 输出电路包括数模转换器，其包括可变寄存器的串联电路和用于产生可变偏置电位的场效应晶体管，多个电流源晶体管和多个转移场晶体管，每个用于选择性地施加可变偏置电位 根据数字信号耦合到相关联的电流源晶体管的栅极; 一个扬声器 以及两对开关晶体管，用于交替地向扬声器提供不同极性的数模转换器的输出电流。

    Constant voltage circuit comprising an IGFET and a transistorized inverter circuit
    2.
    发明授权
    Constant voltage circuit comprising an IGFET and a transistorized inverter circuit 失效
    包括IGFET和晶体管反相电路的恒压电路

    公开(公告)号：US4135125A

    公开(公告)日：1979-01-16

    申请号：US777853

    申请日：1977-03-15

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: G05F3/24 ,  G05F1/56

    CPC classification number: G05F3/247

    Abstract: A constant voltage circuit comprises an IGFET for deriving an output voltage for a load from a power supply and an inverter circuit responsive to the output voltage for controlling the IGFET in a negative feedback manner to stabilize the output voltage against fluctuations in the supply voltage and the load. The IGFET may be a depletion or an enhancement MOSFET. The inverter circuit preferably comprises an enhancement and a depletion or an enhancement MOSFET. Either a resistor or another IGFET may be connected between the inverter circuit and ground. The constant voltage circuit is readily manufactured as an IC together with an IGFET circuit used as the load.

    Abstract translation: 恒压电路包括IGFET，用于根据用于以负反馈方式控制IGFET的输出电压从电源和逆变器电路导出负载的输出电压，以稳定输出电压以抵抗电源电压的波动，并且 加载。 IGFET可以是耗尽或增强的MOSFET。 逆变器电路优选地包括增强和耗尽或增强的MOSFET。 电抗器或另一个IGFET可以连接在逆变器电路和地之间。 恒压电路容易地与用作负载的IGFET电路一起作为IC制造。

    Sound synthesizer
    3.
    发明授权
    Sound synthesizer 失效
    声音合成器

    公开(公告)号：US4577343A

    公开(公告)日：1986-03-18

    申请号：US531195

    申请日：1983-09-12

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: G10L13/06 ,  G10L13/02 ,  G10L21/04 ,  G10L1/08

    CPC classification number: G10L13/02

    Abstract: Speech is synthesized by repeated readout of prestored basic speech waveforms. For varying the speech tone frequency, readout is done at a fixed rate but skipping samples sequentially stored.

    Abstract translation: 通过重复读出预存的基本语音波形来合成语音。 为了改变语音频率，以固定速率进行读出，但是依次存储跳过样本。

    Information processing unit
    4.
    发明授权
    Information processing unit 失效
    信息处理单元

    公开(公告)号：US4470113A

    公开(公告)日：1984-09-04

    申请号：US339223

    申请日：1982-01-13

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: G06F3/00 ,  G06F13/42 ,  G06F15/17 ,  G06F15/177 ,  G06F3/04

    CPC classification number: G06F15/17 ,  G06F13/4204 ,  G06F13/4221 ,  G06F15/177

    Abstract: An information processing unit, such as a central processor, microprocessor or one-chip microcomputer, which can be used as either a master unit or a slave unit yet does not require the provision of extra external terminals for control signals. The unit is provided with first and second bidirectional input/output ports and an internal bus coupled to both of the first and second input/output ports. The input/output mode of the two busses can be controlled either by an internally-generated control signal or by an externally-supplied control signal inputted to the unit. The one of the first and second control signals used for controlling the transmission modes of the input/output ports is determined in accordance with data input through one of the input/output ports and stored internally of the unit.

    Abstract translation: 可以用作主单元或从单元的诸如中央处理器，微处理器或单片微计算机的信息处理单元，但不需要为控制信号提供额外的外部端子。 该单元设置有第一和第二双向输入/输出端口以及耦合到第一和第二输入/输出端口两者的内部总线。 两个总线的输入/输出模式可以由内部产生的控制信号或输入到该单元的外部提供的控制信号来控制。 用于控制输入/输出端口的传输模式的第一和第二控制信号中的一个根据通过输入/输出端口之一输入并存储在单元内部的数据来确定。

    Semiconductor memory device with address generator
    5.
    发明授权
    Semiconductor memory device with address generator 失效
    带地址发生器的半导体存储器

    公开(公告)号：US4841487A

    公开(公告)日：1989-06-20

    申请号：US160983

    申请日：1988-02-26

    Applicant: Shigeki Demura ,  Toshio Oura

    Inventor： Shigeki Demura ,  Toshio Oura

    IPC: G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/408 ,  G11C17/18

    CPC classification number: G11C8/00 ,  G11C7/1006

    Abstract: For improvement in operation speed, there is disclosed a semiconductor memory device comprising a memory cell array associated by a addressing circuit for reading out a plurality of data bits, a series of selector modules operative to decrease in number the data bits stage by stage, a temporary data storage module preserving the data bits fed from the final stage of the selector module and supplying all of the data bits to a destination, and a control circuit operative to produce an internal addressing signal for selection of the data bits, wherein the addressing circuit and the selector module except for the final stage of the selector module are supplied with the internal addressing signal for selection but the final stage of the selector module is directly supplied from the temporary data storage with a part of data bits, thereby realizing a parallel operation for reduction in time period for read-out operation.

    Signal generating circuit
    7.
    发明授权
    Signal generating circuit 失效
    信号发生电路

    公开(公告)号：US4023122A

    公开(公告)日：1977-05-10

    申请号：US651697

    申请日：1976-01-23

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: H03K3/03 ,  H03K3/3565 ,  H03K4/06 ,  H03K5/02 ,  H03K5/08 ,  H03K3/353

    CPC classification number: H03K5/08 ,  H03K3/03 ,  H03K3/3565 ,  H03K4/06 ,  H03K5/023

    Abstract: A signal generating circuit includes a switching circuit that includes two series-connected circuits. Each of the latter includes an enhancement-type MOS FET and a depletion-type MOS FET connected between one terminal of a power source and a junction point of the series-connected circuits. The junction point is used as the output terminal of the switching circuit.

    Abstract translation: 信号发生电路包括一个包括两个串联电路的开关电路。 后者包括连接在电源的一个端子和串联电路的连接点之间的增强型MOS FET和耗尽型MOS FET。 接点用作开关电路的输出端。

    Information processing system capable of indicating tendency to change
    8.
    发明授权
    Information processing system capable of indicating tendency to change 失效
    信息处理系统能够表现出改变的趋势

    公开(公告)号：US06738761B1

    公开(公告)日：2004-05-18

    申请号：US09661379

    申请日：2000-09-13

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: G06F700

    CPC classification number: G06Q50/18 ,  G06F17/30011 ,  G06Q10/10 ,  Y10S707/99933 ,  Y10S707/99945 ,  Y10S715/968

    Abstract: In an information processing system, an information storing unit stores a plurality of main information sets along with time information sets. A retrieval condition input unit inputs retrieval conditions for the main information sets. A retrieval execution unit performs a retrieval upon the main information sets along with the time information sets by using the retrieval conditions. A cell output information generating unit receives retrieved main information sets along with the time information sets and generates a number of the main information sets and a tendency of the number of the main information sets to change with respect to time for each of cells defined by the retrieval conditions. A cell output unit outputs each of the cell and displays each of the cells at a location on a matrix designated by the retrieval conditions.

    Abstract translation: 在信息处理系统中，信息存储单元与时间信息集一起存储多个主要信息集。 检索条件输入单元输入主要信息集的检索条件。 检索执行单元通过使用检索条件与主信息集合一起执行与时间信息集的检索。 单元输出信息生成单元与时间信息集合一起接收检索到的主信息集合，并且生成多个主信息集合以及主信息集合的数量相对于由 检索条件。 单元输出单元输出单元中的每一个，并且在由检索条件指定的矩阵上的位置处显示每个单元。

    Display apparatus for displaying a pattern having a slant portion
    10.
    发明授权
    Display apparatus for displaying a pattern having a slant portion 失效
    用于显示具有倾斜部分的图案的显示装置

    公开(公告)号：US4318097A

    公开(公告)日：1982-03-02

    申请号：US20789

    申请日：1979-03-15

    Applicant: Toshio Oura

    Inventor： Toshio Oura

    IPC: H04N7/18 ,  A63F13/00 ,  G09G5/02 ,  G09G5/24 ,  G09G5/36 ,  H04N5/262 ,  G09G1/14

    CPC classification number: G09G5/24 ,  A63F13/00 ,  H04N5/262 ,  A63F2300/203

    Abstract: A pattern display apparatus in which a pattern is composed of a plurality of rectangular picture elements, picture element signals representing the picture elements are generated from a pattern generator in synchronism with a scanning type display means, and the picture element signals are applied to the scanning type display means thereby to display the pattern thereat comprises means for selectively converting the picture element at a slant portion of the pattern into substantial parallelogram picture element with such slope as to run along the slant line of the slant portion.

    Abstract translation: 一种图案显示装置，其中图案由多个矩形图像元素组成，与扫描型显示装置同步地从图案发生器产生表示图像元素的图像元素信号，并且将图像元素信号施加到扫描 类型显示装置，从而显示图案，其中包括用于选择性地将图案的倾斜部分处的图像元素以这样的斜率沿着倾斜部分的倾斜线行进的基本平行四边形图像元素的装置。

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