Method of manufacturing semiconductor device
    2.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US5238859A

    公开(公告)日:1993-08-24

    申请号:US653482

    申请日:1991-02-12

    摘要: In the selective anisotropic etching by RIE of a first poly-Si film formed on a gate oxide film the poly-Si film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a second poly-Si film, followed by applying RIE. This particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the second poly-Si film and the portion of the first polysilicon film thereunder.

    摘要翻译: 在通过RIE形成的第一多晶硅膜的选择性各向异性蚀刻中,多晶硅膜不完全被去除,使得多晶硅膜部分未被除去。 然后,用第二多晶硅膜覆盖整个表面,然后施加RIE。 该特定技术允许防止多晶硅栅极附近的栅极氧化膜和栅极氧化膜和衬底之间的界面被损坏。 最后,施加不对多晶硅栅极附近的栅极绝缘膜造成损伤的化学干蚀刻,以除去第二多晶硅膜及其下面的第一多晶硅膜的部分。

    Method of manufacturing semiconductor device
    3.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US5032535A

    公开(公告)日:1991-07-16

    申请号:US341175

    申请日:1989-04-21

    摘要: In the selective etching by RIE, a poly-Si film formed on the gate oxide film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a poly-Si film, followed by applying RIE. The particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the poly-Si film.

    摘要翻译: 在通过RIE的选择性蚀刻中,形成在栅极氧化膜上的多晶硅膜不会完全去除,使得多晶硅膜部分地不被去除。 然后,用多晶硅膜覆盖整个表面,然后施加RIE。 特别的技术允许防止多晶硅栅极附近的栅极氧化膜和栅氧化膜和衬底之间的界面被损坏。 最后,施加不会对多晶硅栅极附近的栅极绝缘膜造成损伤的化学干蚀刻,以去除多晶硅膜。

    Method for manufacturing confectionery, freeze drying method and freeze-dried confectionery
    5.
    发明申请
    Method for manufacturing confectionery, freeze drying method and freeze-dried confectionery 审中-公开
    制作糖果,冷冻干燥方法和冷冻干燥糖果的方法

    公开(公告)号:US20060240176A1

    公开(公告)日:2006-10-26

    申请号:US11391514

    申请日:2006-03-28

    IPC分类号: A23G3/00

    摘要: A method for freeze drying confectionary is provided, whereby a confectionary is provided that can be stored for long periods of time without deformation. Further, a confectionery is provided using cream comprising 28 to 33 parts by weight of cream having a milk fat content of 42% to 48%, 28 to 33 parts by weight of cream having a milk fat content of 32% to 38%, 28 to 33 parts by weight of vegetable-based cream, and 5 to 10 parts by weight of sugar. The confectionery is freeze dried by: freezing the confectionery; subsequently setting the drying pressure to 0.60 to 0.65 Torr; performing primary sublimation by drying at a temperature of 25° C. to 40° C., for 3 to 4 hours; subsequently performing secondary sublimation by drying at a temperature of 60° C. to 70° C. for 18 to 20 hours; and further performing tertiary sublimation by drying at a temperature of 35° C. to 45° C. for 1.5 to 4.5 hours.

    摘要翻译: 提供一种冷冻干燥糖果的方法,由此提供可以长时间储存​​而不变形的糖果。 此外,使用含有28〜33重量份乳脂肪含量为42〜48重量%的奶油,28〜33重量份乳脂含量为32〜38重量%的奶油,28 至33重量份的植物性霜剂和5至10重量份的糖。 糖果通过以下方式冻结:冻结糖果; 随后将干燥压力设定为0.60〜0.65乇; 通过在25℃至40℃的温度下干燥3至4小时进行初级升华; 随后通过在60℃至70℃的温度下干燥18至20小时进行二次升华; 并进一步通过在35℃至45℃的温度下干燥1.5至4.5小时进行三次升华。

    Semiconductor device
    6.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号:US20050133921A1

    公开(公告)日:2005-06-23

    申请号:US10975081

    申请日:2004-10-28

    摘要: A semiconductor device comprises a semiconductor substrate, a multilayer interconnect provided on the semiconductor substrate, the multilayer interconnect comprising a plurality of layers of insulating films and interconnects, at least one fuse interconnect provided in a layer higher than the multilayer interconnect, and a moisture absorption preventing hollow member including a hollow structure, the moisture absorption preventing hollow member selectively surrounding the at least one fuse interconnect and reaching a surface of the semiconductor substrate through the multilayer interconnect, the moisture absorption preventing hollow member comprising a material having a lower hygroscopicity than the plurality of layers of insulating films.

    摘要翻译: 半导体器件包括半导体衬底,设置在半导体衬底上的多层互连,多层互连包括多层绝缘膜和互连,设置在比多层互连高的层中的至少一个熔丝互连,以及吸湿 防止中空构件包括中空结构,所述防吸湿中空构件选择性地围绕所述至少一个熔断器互连件并通过所述多层互连件到达所述半导体衬底的表面,所述吸湿防止中空构件包括具有比所述多层互连件更低吸湿性的材料 多层绝缘膜。