公开(公告)号：US4363977A

公开(公告)日：1982-12-14

申请号：US236609

申请日：1981-02-20

申请人： Toshitaka Tsuda ,  Kazuo Murano ,  Kazuo Yamaguchi ,  Takafumi Chujo ,  Norio Murakami ,  Motohide Takahashi

发明人： Toshitaka Tsuda ,  Kazuo Murano ,  Kazuo Yamaguchi ,  Takafumi Chujo ,  Norio Murakami ,  Motohide Takahashi

IPC分类号： G01R19/00 ,  H03K5/24 ,  H04B10/69 ,  H04L25/06 ,  H03K5/153 ,  H03K5/01

CPC分类号： H04B10/695 ,  G01R19/0038 ,  H03K5/2427 ,  H04B10/6911 ,  H04L25/062 ,  H04L25/065

摘要： A device for discriminating between two values of a signal using DC offset compensation including an automatic gain control circuit, a peak detector circuit and a feedback path from the peak detector circuit to the input circuit of the automatic gain control circuit. The value of the feedback current is regulated so that the maximum value of one of the same polarity signals and the opposite polarity signal coincides with the minimum value of the other of the two signals.

摘要翻译： 用于使用包括自动增益控制电路，峰值检测器电路和从峰值检测器电路到自动增益控制电路的输入电路的反馈路径的DC偏移补偿来鉴别信号的两个值的装置。 调节反馈电流的值，使得相同极性信号和相反极性信号之一的最大值与两个信号中另一个的最小值一致。

公开(公告)号：US4347617A

公开(公告)日：1982-08-31

申请号：US210850

申请日：1980-11-26

申请人： Kazuo Murano ,  Kazuo Yamaguchi ,  Norio Murakami ,  Toshitaka Tsuda

发明人： Kazuo Murano ,  Kazuo Yamaguchi ,  Norio Murakami ,  Toshitaka Tsuda

IPC分类号： H04L25/30 ,  H04L25/49 ,  H03K5/26

CPC分类号： H04L25/4906

摘要： An asynchronous transmission system for binary-coded information is disclosed. According to this system, in a transmitting terminal (A), when successive data of the same code in a set of asynchronous data lasts for a predetermined period of time (T.sub.1), a refresh pulse, the polarity of which is opposite to that of the successive data, is added to a transmission signal. However, the addition of such a refresh pulse to the transmission signal is inhibited for a predetermined period of time (T.sub.2) to allow for a change of data. In a receiving terminal (B), a pulse, the width of which is larger or equal to a minimum period of data, and a pulse, the width of which is smaller than or equal to a pulse-width (T.sub.0) of a refresh pulse, can be discriminated and removed by a pulse-width discrimination circuit. As a result, the refresh pulse is not present in the output signal of the pulse-width discrimination circuit. Thus, the original asynchronous data is restored.

摘要翻译： 公开了一种用于二进制编码信息的异步​​传输系统。 根据该系统，在发送终端（A）中，当一组异步数据中的相同代码的连续数据持续预定时间段（T1）时，刷新脉冲的极性与 连续数据被添加到传输信号。 然而，在发送信号中添加这样的刷新脉冲在预定时间段（T2）被禁止以允许数据的改变。 在接收终端（B）中，其宽度大于或等于最小数据周期的脉冲，其宽度小于或等于刷新脉冲宽度（T0）的脉冲 脉冲，可以通过脉冲宽度鉴别电路鉴别和去除。 结果，刷新脉冲不存在于脉冲宽度判别电路的输出信号中。 因此，恢复原始异步数据。

公开(公告)号：US4679188A

公开(公告)日：1987-07-07

申请号：US779639

申请日：1985-09-24

申请人： Misao Fukuda ,  Toshitaka Tsuda ,  Kazuo Murano ,  Yutaka Awata

发明人： Misao Fukuda ,  Toshitaka Tsuda ,  Kazuo Murano ,  Yutaka Awata

IPC分类号： H04L5/14 ,  H04B1/56 ,  H04J3/02 ,  H04L7/00

CPC分类号： H04L5/1492 ,  H04L5/1423

摘要： A digital transmission system comprising at least two transmitting-receiving (T/R) units and a single transmission line connected therebetween. One of the T/R units the first transmits a control signal to the other T/R units with which frame synchronization and timing recovery are carried out using the transmitted control signal. At the same time, the other T/R unit inhibits transmission of send signal therefrom to the first T/R unit. Further, the send signal from one T/R unit to the other T/R unit is transmitted in the form of a frame. Each frame includes, at its end portion, a non-signal duration portion.

摘要翻译： 一种包括至少两个发送接收（T / R）单元和连接在它们之间的单个传输线的数字传输系统。 T / R单元之一首先利用这样传输的控制信号将控制信号发送到执行帧同步和定时恢复的其它T / R单元。 同时，另一个T / R单元禁止发送信号到第一T / R单元。 此外，从一个T / R单元到另一个T / R单元的发送信号以帧的形式发送。 每个帧在其端部包括非信号持续时间部分。

公开(公告)号：US4194243A

公开(公告)日：1980-03-18

申请号：US787494

申请日：1977-04-14

申请人： Toshitaka Tsuda

发明人： Toshitaka Tsuda

IPC分类号： G06F7/00 ,  G06F9/34 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F12/02

摘要： A data processing system for reading or writing data comprises a data memory unit and a processing unit, the data to be read from or written to the data memory unit is being serially transferred bit by bit over a single line connected between the data memory unit and the processing unit. The processing unit is operated in accordance with an instruction specified by instruction addressing information which is produced by an instruction counter. The data is specified by data addressing information which is produced by a means for specifying the address of the data memory unit. Both the lower bits of the data addressing information and the lower bits of the instruction addressing information are jointly produced by the lower bit stages of the instruction counter. The upper bits of the data addressing information are momentarily stored in an upper bits specifying register during one read or write operation while one execution of one data bit data is performed. Further, the data addressing information is provided synchronously with the provision of the instruction addressinginformation. The number of bits of the data word must be equal to or must be a multiple of the number of bits of the instruction word, or the number of bits of the instruction word must be a multiple of the number of bits of the data word.

摘要翻译： 用于读取或写入数据的数据处理系统包括数据存储单元和处理单元，要从数据存储单元读取或写入数据存储单元的数据通过连接在数据存储单元和 处理单元。 处理单元根据由指令计数器产生的指令寻址信息指定的指令进行操作。 数据由通过用于指定数据存储单元的地址的装置产生的数据寻址信息来指定。 数据寻址信息的低位和指令寻址信息的低位由指令计数器的低位级共同产生。 在执行一个数据位数据的一次执行期间，在一个读或写操作期间，数据寻址信息的高位被暂时存储在高位指定寄存器中。 此外，与提供指令寻址信息同步地提供数据寻址信息。 数据字的位数必须等于或必须是指令字的位数的倍数，否则指令字的位数必须是数据字的位数的倍数。

公开(公告)号：US4771439A

公开(公告)日：1988-09-13

申请号：US49048

申请日：1987-05-12

申请人： Takeshi Okazaki ,  Toshitaka Tsuda ,  Shin-ichi Maki ,  Kiichi Matsuda ,  Hirohisa Gambe ,  Hirokazu Fukui ,  Toshi Ikezawa

发明人： Takeshi Okazaki ,  Toshitaka Tsuda ,  Shin-ichi Maki ,  Kiichi Matsuda ,  Hirohisa Gambe ,  Hirokazu Fukui ,  Toshi Ikezawa

IPC分类号： H04N11/04 ,  G06T9/00 ,  H03M3/04 ,  H04B14/06

CPC分类号： H03M7/3044 ,  G06T9/004

摘要： A differential coding circuit including a subtracter, a quantizer for quantizing a differential signal from the subtracter, and a predicted signal generating circuit for generating a predicted signal on the basis of a quantized differential signal from the quantizer. The subtracter subtracts the quantized differential signal of the quantizer and the predicted signal from the sampled input signal. The critical path of the circuit is shortened, therefore the operation speed of the differential coding circuit increases.

摘要翻译： 一种差分编码电路，包括减法器，用于量化来自减法器的差分信号的量化器，以及预测信号产生电路，用于根据来自量化器的量化差分信号产生预测信号。 减法器从采样输入信号中减去量化器的量化差分信号和预测信号。 电路的关键路径缩短，因此差分编码电路的运行速度增加。

公开(公告)号：US4651033A

公开(公告)日：1987-03-17

申请号：US574725

申请日：1984-01-27

申请人： Nobuyuki Yasutake ,  Toshitaka Tsuda

发明人： Nobuyuki Yasutake ,  Toshitaka Tsuda

IPC分类号： H03K17/0412 ,  H03K17/14 ,  H03K17/60 ,  H03K17/30

CPC分类号： H03K17/14 ,  H03K17/04126 ,  H03K17/603

摘要： A differential switching circuit includes a first current switching circuit having a first input terminal; a second current switching circuit having a second input terminal and a threshold different from that of the first circuit; and a constant current source commonly connected to the first and second circuits. Complementary input signals are applied to the first and second input terminals.

摘要翻译： 差分开关电路包括具有第一输入端的第一电流开关电路; 第二电流开关电路，具有与第一电路不同的第二输入端和阈值; 以及通常连接到第一和第二电路的恒流源。 互补输入信号被施加到第一和第二输入端子。

公开(公告)号：US5056121A

公开(公告)日：1991-10-08

申请号：US326175

申请日：1989-03-20

申请人： Shinji Ohta ,  Misao Fukuda ,  Toshitaka Tsuda

发明人： Shinji Ohta ,  Misao Fukuda ,  Toshitaka Tsuda

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC分类号： H04L7/0062 ,  H04L7/0004

摘要： A circuit for obtaining accurate timing information from a received signal, first, obtains an impulse response at a certain phase, which phase is determined based on a reference phase of a receiver clock, and then the obtained impulse response is compared with a reference level. As the reference level: a predetermined value just below the maximum value of the overall impulse response; an impulse response at another phase; or an impulse response at the same phase in a previous period, is used. The reference phase is controlled, according to the result of the comparison.

公开(公告)号：US4668987A

公开(公告)日：1987-05-26

申请号：US710380

申请日：1985-03-11

申请人： Kiichi Matsuda ,  Toshitaka Tsuda ,  Toshihiro Homma ,  Hiroshi Fukuda ,  Takeshi Okazaki ,  Shin-ichi Maki

发明人： Kiichi Matsuda ,  Toshitaka Tsuda ,  Toshihiro Homma ,  Hiroshi Fukuda ,  Takeshi Okazaki ,  Shin-ichi Maki

IPC分类号： G06T7/20 ,  H04N7/36 ,  H04N7/12 ,  H04N7/18

CPC分类号： G06T7/2013 ,  H04N19/152 ,  H04N19/43 ,  H04N19/50 ,  H04N19/51 ,  G06T2207/10016

摘要： An apparatus for band compression processing of a picture signal which generates forecasting error signal and movement vector and updates only the movement vector during a comb-out operation. During comb-out processing, a picture signal is recirculated while the movement vector is produced and accumulated. At the end of the comb-out processing, the change in the movement vector from the accumulated vector is within a desired range. Therefore, the scale of a circuit for detecting the movement vector after the comb-out operation does not increase.

摘要翻译： 一种用于产生预测误差信号和运动矢量的图像信号的频带压缩处理的装置，并且在梳理操作期间仅更新运动矢量。 在梳理处理期间，在产生和累积运动矢量的同时，图像信号被再循环。 在梳理处理结束时，来自累积矢量的运动矢量的变化在期望的范围内。 因此，用于检测梳理操作之后的运动矢量的电路的比例不增加。