公开(公告)号：US20050235245A1

公开(公告)日：2005-10-20

申请号：US11012613

申请日：2004-12-16

申请人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/00 ,  H01L21/027 ,  H01L21/82

CPC分类号： G06F17/5081

摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.

摘要翻译： 公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状 对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的 值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

公开(公告)号：US07266801B2

公开(公告)日：2007-09-04

申请号：US11012613

申请日：2004-12-16

申请人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.

摘要翻译： 公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状 对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的 值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

公开(公告)号：US07194704B2

公开(公告)日：2007-03-20

申请号：US11012491

申请日：2004-12-16

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

CPC分类号： G06F17/5081 ,  H01L21/0271

摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

摘要翻译： 公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分 在维修准则上。

公开(公告)号：US20050204322A1

公开(公告)日：2005-09-15

申请号：US11012491

申请日：2004-12-16

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82

CPC分类号： G06F17/5081 ,  H01L21/0271

摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

摘要翻译： 公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分 在维修准则上。

公开(公告)号：US07996794B2

公开(公告)日：2011-08-09

申请号：US11945697

申请日：2007-11-27

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

摘要翻译： 公开了一种校正层次结构的掩模数据处理方法。 在具有包括多个单元的设计数据的设计数据中，每个单元均具有设计图案时，当要执行掩模数据处理的计算的设计图案的总数或总边沿长度时 如果对具有初始层次结构的设计数据执行掩模数据处理的计算，则修正了要执行的计算量或扩展度等于或大于预定阈值等于或大于预定阈值。 执行该校正以减少要执行计算的设计模式的总数或总边缘长度，即要执行的计算量，扩展度。

公开(公告)号：US20110265047A1

公开(公告)日：2011-10-27

申请号：US13067810

申请日：2011-06-28

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

公开(公告)号：US20100021825A1

公开(公告)日：2010-01-28

申请号：US12478479

申请日：2009-06-04

申请人： Chikaaki KODAMA ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

发明人： Chikaaki KODAMA ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A mask pattern data creation method includes: determining whether or not a spacing of adjacent assist pattern feature data is not more than a prescribed spacing, based on: initial position data indicating an initially set position of the assist pattern feature data determined based on an illumination condition; and initial size data indicating an initially set size of the assist pattern feature data satisfying a size condition to not optically form an image on the transfer destination; and moving at least one of the adjacent assist pattern feature data or reducing a size of the at least one to increase the spacing of the assist pattern feature data to exceed a prescribed spacing in the case where it is determined that the spacing of the assist pattern feature data is not more than the prescribed spacing.

摘要翻译： 掩模图案数据创建方法包括：基于：基于指示基于照明确定的辅助图案特征数据的初始设置位置的初始位置数据来确定相邻辅助图案特征数据的间隔是否不大于规定间距 条件; 以及初始尺寸数据，其指示辅助图案特征数据的初始设置尺寸，其满足不在转印目的地上光学地形成图像的尺寸条件; 以及在确定所述辅助图案的间距的情况下，移动所述相邻辅助图案特征数据中的至少一个或减小所述至少一个的尺寸以增加所述辅助图案特征数据的间隔超过规定间隔 特征数据不超过规定的间距。

公开(公告)号：US07614026B2

公开(公告)日：2009-11-03

申请号：US11521440

申请日：2006-09-15

申请人： Toshiya Kotani ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A pattern of a desired size is formed on a semiconductor substrate by the following procedure. A property, including at least one of an aberration of an exposure device, a property of an illumination, a property of a projection lens, and a pattern coverage in a shot, are allocated, in a first database, to predetermined positions assigned in a chip. A second database is prepared by pairing a cell name of a cell extracted from hierarchical processing of a design pattern and arrangement positional data of the cell. The property data is allocated to the cell based on the first and second databases. Mask data processing based on at least one of the property data is executed, and the cell subjected to the mask data processing is rearranged on the chip.

摘要翻译： 通过以下步骤在半导体衬底上形成期望尺寸的图案。 在第一数据库中，将包括曝光装置的像差，照明特性，投影透镜的特性和图案覆盖率中的至少一个的属性分配给第一数据库中指定的预定位置 芯片。 通过配置从设计图案的分层处理提取的单元的单元名称和单元的排列位置数据来准备第二数据库。 基于第一和第二数据库将属性数据分配给小区。 执行基于属性数据中的至少一个的掩模数据处理，并且经受掩模数据处理的单元被重新排列在芯片上。

公开(公告)号：US20070066025A1

公开(公告)日：2007-03-22

申请号：US11521440

申请日：2006-09-15

申请人： Toshiya Kotani ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Hirotaka Ichikawa

IPC分类号： H01L21/76 ,  H01L21/22 ,  H01L21/38

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A pattern forming method for forming a pattern of a desired size on a substrate of a semiconductor device, includes preparing a first database by allocating property data to each position in a chip when the pattern is exposed, preparing a second database by pairing a cell name of a cell extracted from hierarchical processing of a design pattern and arrangement positional data of the cell, by allocating the property data to the cell based on the first database and the second database, executing mask data processing based on at least one of the property data, and rearranging on the chip the cell subjected to the mask data processing.

摘要翻译： 一种用于在半导体器件的衬底上形成期望尺寸的图案的图案形成方法，包括：通过在图案曝光时将特性数据分配给芯片中的每个位置来准备第一数据库，通过将单元名称 通过基于所述第一数据库和所述第二数据库将所述属性数据分配给所述单元，基于所述属性数据中的至少一个执行掩模数据处理，从所述设计模式的分层处理提取的单元和所述单元的排列位置数据 并且在芯片上重新排列经受掩模数据处理的单元。

公开(公告)号：US07998642B2

公开(公告)日：2011-08-16

申请号：US12478479

申请日：2009-06-04

申请人： Chikaaki Kodama ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

发明人： Chikaaki Kodama ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A mask pattern data creation method includes: determining whether or not a spacing of adjacent assist pattern feature data is not more than a prescribed spacing, based on: initial position data indicating an initially set position of the assist pattern feature data determined based on an illumination condition; and initial size data indicating an initially set size of the assist pattern feature data satisfying a size condition to not optically form an image on the transfer destination; and moving at least one of the adjacent assist pattern feature data or reducing a size of the at least one to increase the spacing of the assist pattern feature data to exceed a prescribed spacing in the case where it is determined that the spacing of the assist pattern feature data is not more than the prescribed spacing.

摘要翻译： 掩模图案数据创建方法包括：基于：基于指示基于照明确定的辅助图案特征数据的初始设置位置的初始位置数据来确定相邻辅助图案特征数据的间隔是否不大于规定间距 条件; 以及初始尺寸数据，其指示辅助图案特征数据的初始设置尺寸，其满足不在转印目的地上光学地形成图像的尺寸条件; 以及在确定所述辅助图案的间距的情况下，移动所述相邻辅助图案特征数据中的至少一个或减小所述至少一个的尺寸以增加所述辅助图案特征数据的间隔超过规定间隔 特征数据不超过规定的间距。