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    Semiconductor memory device
    2.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20070165468A1

    公开(公告)日：2007-07-19

    申请号：US11716710

    申请日：2007-03-12

    申请人： Toshiyuki Nishihara ,  Yoshio Sakai

    发明人： Toshiyuki Nishihara ,  Yoshio Sakai

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

    摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

    摘要翻译： 一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器的缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域， 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储更宽范围的有缺陷的存储器的地址。 为此，可以有效地修复随机发生的缺陷。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07385863B2

    公开(公告)日：2008-06-10

    申请号：US11716710

    申请日：2007-03-12

    申请人： Toshiyuki Nishihara ,  Yoshio Sakai

    发明人： Toshiyuki Nishihara ,  Yoshio Sakai

    IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K19/003

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

    摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

    摘要翻译： 一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域， 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储较宽范围的有缺陷的存储器的地址。 为此，可以有效地修复随机发生的缺陷。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US07248514B2

    公开(公告)日：2007-07-24

    申请号：US11000048

    申请日：2004-12-01

    申请人： Toshiyuki Nishihara ,  Yoshio Sakai

    发明人： Toshiyuki Nishihara ,  Yoshio Sakai

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

    摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

    Semiconductor memory device
    6.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20050128830A1

    公开(公告)日：2005-06-16

    申请号：US11000048

    申请日：2004-12-01

    申请人： Toshiyuki Nishihara ,  Yoshio Sakai

    发明人： Toshiyuki Nishihara ,  Yoshio Sakai

    IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C8/00 ,  G11C8/06 ,  G11C29/00 ,  G11C29/44

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

    摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

    摘要翻译： 一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器的缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域， 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储较宽范围的有缺陷的存储器的地址。 为此，可以有效地修复随机发生的缺陷。

    Storage device, computer system, and storage system
    8.
    发明授权
    Storage device, computer system, and storage system 有权
    存储设备，计算机系统和存储系统

    公开(公告)号：US09183132B2

    公开(公告)日：2015-11-10

    申请号：US11493904

    申请日：2006-07-27

    申请人： Toshiyuki Nishihara

    发明人： Toshiyuki Nishihara

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7205

    摘要： A storage device enabling realization of a new storage configuration enabling apparent elimination of the overhead and enabling high speed access all the time particularly when constructing a high parallel configured high speed flash memory system, that is, a storage device having a flash memory as a main storage and having the function of rewriting at least a partial region of the flash memory by additional writing update data in an empty region and invalidating original data and, at the time of standby of the device where there is no access from the outside, performing processing for automatically restoring the invalidated region to an empty region, and a computer system and a storage system using the same.

    摘要翻译： 一种存储装置，其能够实现新的存储配置，从而明显地消除开销并且始终实现高速访问，特别是在构建高并行配置的高速闪速存储器系统时，即具有闪速存储器作为主要的存储装置 存储并且具有通过在空白区域中附加写入更新数据来重新写入闪速存储器的至少部分区域的功能，并且使原始数据无效，并且在不存在来自外部的设备的待机时，执行处理 用于将无效区域自动恢复到空白区域，以及使用该区域的计算机系统和存储系统。

    IMAGING DEVICE AND CAMERA SYSTEM
    9.
    发明申请
    IMAGING DEVICE AND CAMERA SYSTEM 有权
    成像设备和摄像机系统

    公开(公告)号：US20120081589A1

    公开(公告)日：2012-04-05

    申请号：US13241758

    申请日：2011-09-23

    申请人： Toshiyuki Nishihara

    发明人： Toshiyuki Nishihara

    IPC分类号： H04N5/335 ,  H01L27/146

    CPC分类号： H04N5/37455 ,  G01J1/44 ,  G01J2001/444 ,  H04N5/32 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/357 ,  H04N5/363 ,  H04N5/3742 ,  H04N5/378

    摘要： An imaging device includes: a pixel array section functioning as a light receiving section which includes photoelectric conversion devices and in which a plurality of pixels, which output electric signals when photons are incident, are disposed in an array; a sensing circuit section in which a plurality of sensing circuits, which receive the electric signals from the pixels and perform binary determination regarding whether or not there is an incidence of photons on the pixels in a predetermined period, are arrayed; and a determination result integration circuit section having a function of integrating a plurality of determination results of the sensing circuits for the respective pixels or for each pixel group, wherein the determination result integration circuit section derives the amount of photon incidence on the light receiving section by performing photon counting for integrating the plurality of determination results in the plurality of pixels.

    摘要翻译： 成像装置包括：作为包含光电转换装置的光接收部的像素阵列部，其中在光子入射时输出电信号的多个像素排列成阵列; 感测电路部分，其中接收来自像素的电信号并且执行关于在预定周期中是否存在像素的光子入射的二进制确定的多个感测电路被排列; 以及确定结果积分电路部分，其具有对各像素或每个像素组的感测电路的多个确定结果进行积分的功能，其中确定结果积分电路部分通过以下方式导出光接收部分上的光子入射量 执行用于将所述多个确定结果集成在所述多个像素中的光子计数。

    PIXEL CIRCUIT, SOLID-STATE IMAGE PICKUP DEVICE, AND CAMERA
    10.
    发明申请
    PIXEL CIRCUIT, SOLID-STATE IMAGE PICKUP DEVICE, AND CAMERA 有权
    像素电路，固态图像拾取器件和摄像机

    公开(公告)号：US20110205416A1

    公开(公告)日：2011-08-25

    申请号：US13126790

    申请日：2009-11-25

    申请人： Toshiyuki Nishihara

    发明人： Toshiyuki Nishihara

    IPC分类号： H04N5/335

    CPC分类号： H04N5/3745 ,  H01L27/14609 ,  H04N5/3559

    摘要： A pixel circuit has first, second, and third field effect transistors integrated and connected in series from a photoelectric conversion element to a side of an amplifier circuit. The first and second field effect transistors have gate electrodes to be simultaneously collectively driven. A threshold voltage of the first field effect transistor is set to be higher than that of the second field effect transistor. As the gate electrodes are driven step by step, electrons generated by the photoelectric conversion element and transferred via the first field effect transistor are accumulated in a channel region of the second field effect transistor. The electrons accumulated in the channel region are transferred to an input of the amplifier circuit via the third field effect transistor.

    摘要翻译： 像素电路具有从光电转换元件串联连接到放大器电路侧的第一，第二和第三场效应晶体管。 第一和第二场效应晶体管具有同时共同驱动的栅电极。 第一场效应晶体管的阈值电压被设定为高于第二场效应晶体管的阈值电压。 随着门电极逐步驱动，由光电转换元件产生并通过第一场效应晶体管传送的电子被累积在第二场效应晶体管的沟道区中。 积累在沟道区中的电子经由第三场效应晶体管传送到放大器电路的输入端。