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公开(公告)号：US20060156153A1
公开(公告)日：2006-07-13
申请号：US11012979
申请日：2004-12-14
CPC分类号： G06F11/0721 , G06F11/0793
摘要： An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
摘要翻译： 处理器的错误处理程序，响应于处理器的第一检测到的不可恢复错误（DUE）执行，响应于通过评估第二DUE对错误处理例程的正确性的影响而发生第二DUE的指示 。
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公开(公告)号：US20060075301A1
公开(公告)日：2006-04-06
申请号：US10948904
申请日：2004-09-24
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3824 , G06F9/3861 , G06F11/0715 , G06F11/1016 , G06F11/1032
摘要： An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
摘要翻译： 一种装置包括收集与一个或多个处理相关联的存储指令信息的缓冲器。 收集的存储指令信息包括要存储数据的数据和地址。 该装置还包括缓冲器控制，其在收集与第二进程相关联的存储指令之前，将与第一进程相关联的存储指令的缓冲器排出。
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公开(公告)号：US20070079036A1
公开(公告)日：2007-04-05
申请号：US11241623
申请日：2005-09-30
申请人： Shubhendu Mukherjee
发明人： Shubhendu Mukherjee
IPC分类号： G06F13/368
CPC分类号： G06F1/3203 , G06F1/3287 , G06F13/36 , Y02D10/171
摘要： Methods and apparatus to reduce power consumption in arbiters of interconnection routers are described. In one embodiment, an arbiter may be turned off for a select number of clock cycles if no arbitration is to be performed on the corresponding buffer.
摘要翻译： 描述了在互连路由器仲裁器中降低功耗的方法和装置。 在一个实施例中，如果不对对应的缓冲器执行仲裁，仲裁器可以被关闭选择数量的时钟周期。
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公开(公告)号：US20060095821A1
公开(公告)日：2006-05-04
申请号：US10953887
申请日：2004-09-29
IPC分类号： G06F9/44
CPC分类号： G06F11/1494 , G06F11/1695
摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要翻译： 描述用于冗余多线程环境中的检查指令的方法和装置。 在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。 检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。 然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。 如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。
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公开(公告)号：US20050268028A1
公开(公告)日：2005-12-01
申请号：US10852420
申请日：2004-05-25
申请人： Shubhendu Mukherjee
发明人： Shubhendu Mukherjee
CPC分类号： G11C15/00 , G06F12/0897
摘要： A parallel lookup memory (PLM) is provided. The PLM includes a content addressable memory (CAM) array having a plurality of CAM entries. Each CAM entry has at least two storage location, and one of the locations includes value matching logic. The PLM also includes a PLM controller, which, responsive to an external command, applies a search value to a sub-set of the CAM entries. The sub-set and search values are identified by the external command, which includes data identifying CAM entries that are a start and end location of the sub-set, or data identifying a CAM entries that is a start of the sub-set and a length identifier representing a number of CAM entries to be searched. The PLM may be provided in a processor core, in a processor chip external to a processor core as a counterpart to a layer of cache, or in a multiprocessor computer system having a number of agents coupled to an external communication bus, where the PLM is provided in a first agent and a processor is provided in a second agent.
摘要翻译： 提供了一个并行查找存储器（PLM）。 PLM包括具有多个CAM条目的内容可寻址存储器（CAM）阵列。 每个CAM条目具有至少两个存储位置，并且其中一个位置包括值匹配逻辑。 PLM还包括PLM控制器，响应于外部命令，将一个搜索值应用于CAM条目的子集。 子集和搜索值由外部命令标识，外部命令包括识别作为子集的开始和结束位置的CAM条目的数据，或标识作为子集的开始的CAM条目的数据，以及 表示要搜索的CAM条目的数量的长度标识符。 PLM可以设置在处理器核心中，处理器核心外部的处理器芯片中，作为高速缓存层的对应，或者在具有耦合到外部通信总线的多个代理的多处理器计算机系统中，其中PLM是 提供在第一代理中并且处理器被提供在第二代理中。
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公开(公告)号：US20050198437A1
公开(公告)日：2005-09-08
申请号：US10796520
申请日：2004-03-08
申请人： Shubhendu Mukherjee
发明人： Shubhendu Mukherjee
CPC分类号： G06F12/0813 , G06F12/0828 , G06F12/0859
摘要： The ability to combine a plurality of remote read miss requests and/or a plurality of exclusive access requests into a single network packet for efficiently utilizing network bandwidth. This combination exists for a plurality of processors in a network configuration. In contrast, other solutions have inefficiently utilized network bandwidth by individually transmitting a plurality of remote read miss requests and/or a plurality of exclusive access requests via a plurality of network packets.
摘要翻译： 将多个远程读取未命中请求和/或多个独占访问请求组合到单个网络分组中以有效利用网络带宽的能力。 这种组合存在于网络配置中的多个处理器。 相比之下，其他解决方案通过经由多个网络分组单独发送多个远程读取未命中请求和/或多个独占访问请求而无效地利用网络带宽。
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公开(公告)号：US07849387B2
公开(公告)日：2010-12-07
申请号：US12148812
申请日：2008-04-23
IPC分类号： H03M13/00
CPC分类号： G06F11/3466 , G06F11/3409 , G06F2201/88 , Y02D10/34
摘要： In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，提供量子检测器，用于基于与量化期间的处理器结构的操作相关联的处理器度量，以及基于所述漏洞测量来控制误差减轻单元的控制器，来检测处理器的脆弱性度量。 描述和要求保护其他实施例。
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8.发明申请Method and apparatus for lockstep processing on a fixed-latency interconnect 有权在固定延迟互连上进行锁步处理的方法和装置公开(公告)号：US20070168712A1
公开(公告)日：2007-07-19
申请号：US11282213
申请日：2005-11-18
IPC分类号： G06F11/00
CPC分类号： G06F11/1683 , G06F11/1637
摘要： Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.
摘要翻译： 描述并要求保护在每个设备上生成请求，比较请求以及将匹配请求转发到服务节点的锁步骤中的两个或多个设备的操作方法。 还描述并要求保护使用该方法的冗余执行系统。
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9.发明申请Implementation to save and restore processor registers on a context switch 审中-公开实现在上下文切换中保存和恢复处理器寄存器公开(公告)号：US20060149940A1
公开(公告)日：2006-07-06
申请号：US11024358
申请日：2004-12-27
申请人： Shubhendu Mukherjee
发明人： Shubhendu Mukherjee
IPC分类号： G06F9/44
CPC分类号： G06F9/461 , G06F9/30105 , G06F9/3826 , G06F9/3842 , G06F9/3865
摘要： A method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand. In one embodiment, when OS switches to a new process, the processor saves only those registers that have been modified in the current process. The processor may not bring in these registers for the new process, rather, the processor will load them on demand. If instructions from the new process do not locate their source operand in the register file, it will initiate a miss handling flow for the register and restore the register value in the register file. Then the pipeline will reissue the instruction that missed in the register file.
摘要翻译： 一种用于使处理器能够逐步且按需地在上下文切换上执行保存和恢复的方法和装置。 在一个实施例中，当OS切换到新进程时，处理器仅保存在当前进程中被修改的那些寄存器。 处理器可能不会为这些新进程引入这些寄存器，而是处理器将按需加载它们。 如果新进程的指令没有将其源操作数定位在寄存器文件中，它将启动寄存器的未命中处理流程，并将寄存器值恢复到寄存器文件中。 然后管道将重新发出寄存器文件中遗漏的指令。
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10.发明申请Reducing false error detection in a microprocessor by tracking instructions neutral to errors 有权通过跟踪中性到错误的指令，减少微处理器中的错误检测公开(公告)号：US20050283685A1
公开(公告)日：2005-12-22
申请号：US10871429
申请日：2004-06-17
CPC分类号： G06F11/0721 , G06F9/30145 , G06F9/30181 , G06F9/3865 , G06F11/0751 , G06F11/1052 , G06F11/1407
摘要： A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
摘要翻译： 通过跟踪中性到错误的指令来减少微处理器中的错误检测的技术。 当指令被解码时，反码比特被标记到解码指令。 当检测到奇偶校验错误时，指令队列首先检查反pi位是否被设置。 如果反pi位被置位，则指令对于错误是中性的，并且不需要设置pi位。 预取，分支预测提示和NOP是对错误中立的指令类型。
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