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1.发明授权Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard 有权将指令的操作数与重放记分板进行比较，以检测指令重放并将重播记分板复制到问题记分牌公开(公告)号：US06976152B2
公开(公告)日：2005-12-13
申请号：US10066941
申请日：2002-02-04
申请人： Tse-Yu Yeh , David A. Kruckemyer , Randel P. Blake-Campos , Robert Rogenmoser , Robert Stepanian
发明人： Tse-Yu Yeh , David A. Kruckemyer , Randel P. Blake-Campos , Robert Rogenmoser , Robert Stepanian
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.
摘要翻译： 用于处理器的装置包括第一记分板，第二记分板和耦合到第一记分板和第二记分板的控制电路。 控制电路被配置为响应于将第一指令发布到第一管道中而更新第一记分板以指示针对第一指令的第一目的地寄存器的等待写入。 控制电路被配置为响应于通过流水线的第一级的第一指令，更新第二记分板以指示该第一目的地寄存器的写暂停。 在第一阶段可能会发出给定指令的重播信号。 响应于第二指令的重放，控制电路被配置为将第二记分板的内容复制到第一记分板。 在各种实施例中，附加记分板可用于检测不同类型的依赖性。
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2.发明授权Inhibiting of a co-issuing instruction in a processor having different pipeline lengths 失效在具有不同流水线长度的处理器中禁止共同发布指令公开(公告)号：US07269714B2
公开(公告)日：2007-09-11
申请号：US10066984
申请日：2002-02-04
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3806 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3863 , G06F9/3867 , G06F9/3873
摘要： A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.
摘要翻译： 描述了包括第一管线，第二管线和控制电路的处理器。 第一条流水线包括第一阶段，指令结果承诺到架构状态。 第一阶段与第一批管道的问题阶段分开第一阶段。 第二流水线包括第二阶段，在该第二阶段可以报告异常，其中第二阶段与第二流水线的问题阶段分离大于第一数量的第二数量级。 如果第一指令在程序顺序中的第二指令之后，则控制电路被配置为禁止向第一流水线共同发出第一指令，并且向第二流水线发送第二指令。
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公开(公告)号：US07100064B2
公开(公告)日：2006-08-29
申请号：US10158468
申请日：2002-05-30
申请人： Robert Rogenmoser , Michael C. Kim , Tse-Yu Yeh
发明人： Robert Rogenmoser , Michael C. Kim , Tse-Yu Yeh
CPC分类号： G06F9/3869 , G06F9/30189 , G06F9/3836
摘要： An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit. The processor responds to a blown state of the fuse by executing, during use, fewer instructions per period of time than the processor would otherwise execute.
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4.发明申请公开(公告)号：US20050149698A1
公开(公告)日：2005-07-07
申请号：US11069375
申请日：2005-03-01
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.
摘要翻译： 用于处理器的装置包括第一记分板，第二记分板和耦合到第一记分板和第二记分板的控制电路。 控制电路被配置为响应于将第一指令发布到第一管道中而更新第一记分板以指示针对第一指令的第一目的地寄存器的等待写入。 控制电路被配置为响应于通过流水线的第一级的第一指令，更新第二记分板以指示该第一目的地寄存器的写暂停。 在第一阶段可能会发出给定指令的重播信号。 响应于第二指令的重放，控制电路被配置为将第二记分板的内容复制到第一记分板。 在各种实施例中，附加记分板可用于检测不同类型的依赖性。
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公开(公告)号：US20120110392A1
公开(公告)日：2012-05-03
申请号：US13345260
申请日：2012-01-06
申请人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
发明人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
IPC分类号： G06F11/30
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/30145 , G06F9/3832 , G06F9/3861
摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
摘要翻译： 在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。 电路被配置为预测存储器操作是否不对准。 由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。 在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。 存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。 控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。
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6.发明授权Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions 有权通过比较预测和条件选择的暂定目标地址和分支条件的验证来验证群集中的分支的预测公开(公告)号：US06304960B1
公开(公告)日：2001-10-16
申请号：US09130380
申请日：1998-08-06
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/322 , G06F9/325 , G06F9/3806 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the determined target addresses is selected, using predicted branch directions. The selected target address is compared with a predicted target address, and resolved branch directions are compared with predicted branch directions. A misprediction is indicated if either comparison fails.
摘要翻译： 用于验证分支指令簇的分支预测的系统包括地址验证模块和条件验证模块。 地址验证模块确定集群中分支的目标地址。 使用预测的分支方向选择确定的目标地址之一。 将所选择的目标地址与预测的目标地址进行比较，并将分辨的分支方向与预测的分支方向进行比较。 如果比较失败，则会显示错误预测。
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公开(公告)号：US06282636B1
公开(公告)日：2001-08-28
申请号：US09221197
申请日：1998-12-23
申请人： Tse-Yu Yeh , Gregory Mathews , Steven Tu
发明人： Tse-Yu Yeh , Gregory Mathews , Steven Tu
IPC分类号： G06F938
CPC分类号： G06F9/3861
摘要： A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit generates local commit signals, using order information for the instruction in an issue group and any local exception signals it receives. The local commit signals are combined to generate a global commit signal for each instruction in the issue group. Local exception signals are collected at a selected one of the local exception units and processed to generate a global exception unit. The selected local exception unit resteers control of the processing resources to an exception handler associated with the global exception unit.
摘要翻译： 分散式异常处理系统包括多个局部异常单元。 每个局部异常单元被耦合以处理来自其附近的一个或多个处理资源的局部异常信号。 每个本地异常单元使用发布组中的指令的顺序信息和其接收的任何本地异常信号来生成本地提交信号。 组合本地提交信号以为问题组中的每个指令生成全局提交信号。 本地异常信号在选定的一个局部异常单元处收集，并被处理以产生全局异常单元。 所选择的本地异常单元将处理资源的控制恢复到与全局异常单元相关联的异常处理器。
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8.发明授权公开(公告)号：US06240510B1
公开(公告)日：2001-05-29
申请号：US09130387
申请日：1998-08-06
IPC分类号： G06F915
CPC分类号： G06F9/3885 , G06F9/30094 , G06F9/325 , G06F9/3806 , G06F9/3844
摘要： A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target address, and any side effects. Linking logic receives the resolved branch information and identifies a first branch instruction in execution order for which the branch direction is taken.
摘要翻译： 提供一种用于同时处理指令束中的一个或多个分支指令的系统。 该系统包括多个分支执行流水线，每个分支执行流水线能够执行分支指令以确定分支方向，目标地址和任何副作用。 链接逻辑接收解析的分支信息，并以执行分支方向的执行顺序识别第一分支指令。
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9.发明授权Method and apparatus for performing early branch prediction in a microprocessor 失效用于在微处理器中执行早期分支预测的方法和装置公开(公告)号：US06185676B2
公开(公告)日：2001-02-06
申请号：US08940435
申请日：1997-09-30
IPC分类号： G06F1500
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having at least a first entry configured to hold at least a part of a memory address of a pre-selected branch instruction and at least a part of a memory address of a branch target corresponding to the pre-selected branch instruction. The branch prediction unit compares an instruction pointer of an instruction to be executed with the memory address of the pre-selected branch instruction. In response to a match between the instruction pointer and the memory address of pre-selected branch instruction, the unit causes the microprocessor to fetch an instruction corresponding to the branch target. In one embodiment, the instruction pointer generation stage of the microprocessor is implemented as a first stage of the pipelined microprocessor. In addition, the branch prediction unit is compares the instruction pointer and the memory address of the pre-selected branch instruction during a single clock cycle in which the instruction pointer is generated.
摘要翻译： 具有在微处理器的指令指针生成级中实现的分支预测单元的流水线微处理器。 分支预测单元包括具有至少第一条目的存储器件，其被配置为保持预选择的转移指令的存储器地址的至少一部分以及与预选择的转移指令对应的分支目标的存储器地址的至少一部分， 选择分支指令。 分支预测单元将要执行的指令的指令指针与预先选择的分支指令的存储器地址进行比较。 响应于指令指针和预先选择的分支指令的存储器地址之间的匹配，单元使微处理器获取与分支目标相对应的指令。 在一个实施例中，微处理器的指令指针生成级被实现为流水线微处理器的第一级。 此外，分支预测单元在生成指令指针的单个时钟周期期间比较指令指针和预先选择的分支指令的存储器地址。
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10.发明授权Electronic system and method for maintaining synchronization of multiple front-end pipelines 失效用于保持多个前端管道同步的电子系统和方法
公开(公告)号：US6044456A
公开(公告)日：2000-03-28
申请号：US002774
申请日：1998-01-05
IPC分类号： G06F9/38
CPC分类号： G06F9/3869
摘要： A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.
摘要翻译： 描述了一种用于维持通过并行操作的多个前端管道传播的信息的同步的系统和方法。 通常，这些多个前端管道响应于失速状态而变得异步，并且通过冲洗两个前端管道以及通过在不同的时间段内选择性地将这些前端管道从其失速状态中选择性地释放而重新建立同步。
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