公开(公告)号：US06731535B1

公开(公告)日：2004-05-04

申请号：US10455523

申请日：2003-06-06

申请人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

发明人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

IPC分类号： G11C1114

CPC分类号： H01L27/224 ,  G11C11/16 ,  H01L27/228

摘要： A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.

摘要翻译： 非易失性半导体存储器件包括硅衬底，位线，字线和存储单元。 位线位于硅衬底的主表面上方，并且字线被提供以与位线相交。 存储单元位于位线和字线相交的区域，并且其一端电连接到位线，另一端电连接到字线。 存储单元包括串联电连接的TMR元件和存取二极管。 存取二极管包括n型硅层和通过熔融重结晶重结晶的p型硅层，并且在n型硅层和p型硅层之间的界面处具有pn结。 结果，可以廉价地制造尺寸减小并且具有高性能的非易失性半导体存储器件。

公开(公告)号：US07313014B2

公开(公告)日：2007-12-25

申请号：US11188089

申请日：2005-07-25

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

摘要： Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.

摘要翻译： 被设计为具有与MTJ存储单元相同的尺寸和结构的形状虚设单元在MTJ存储单元阵列的外围部分中另外提供，其中用于存储数据的正常MTJ存储单元以矩阵形式布置。 依次布置MTJ存储单元和形状虚设单元，使整个整体具有均匀的间距。 因此，可以消除由于周围的存储单元的高密度和低密度而在制造之后的MTJ存储单元阵列的中心部分的MTJ存储单元和边界部分之间的不均匀性。

公开(公告)号：US07099229B2

公开(公告)日：2006-08-29

申请号：US11063614

申请日：2005-02-24

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C8/00

CPC分类号： G11C11/16 ,  G11C5/147

摘要： A memory block is divided into block units for which parallel data write is performed. Current supply sections capable of supplying a power supply voltage and a ground voltage are provided for block units, independently of one another. With this configuration, in each block unit, writing of data to a selected memory cell is performed by a data write current from the independent current supply section connected to the power supply voltage and the ground voltage. That is, wiring lengths of power supply lines for supplying the power supply voltage and the ground voltage can be shortened. It is therefore possible to suppress a wiring resistance of the power supply line and to supply a desired data write current.

摘要翻译： 存储器块被划分为执行并行数据写入的块单元。 为块单元提供能够提供电源电压和接地电压的电流供应部分彼此独立地设置。 利用这种配置，在每个块单元中，通过来自连接到电源电压和接地电压的独立电流供应部分的数据写入电流来执行将数据写入所选择的存储器单元。 也就是说，可以缩短用于提供电源电压和接地电压的电源线的布线长度。 因此，可以抑制电源线的布线电阻并提供期望的数据写入电流。

公开(公告)号：US20060187736A1

公开(公告)日：2006-08-24

申请号：US11391227

申请日：2006-03-29

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C8/00

CPC分类号： G11C13/0069 ,  G11C7/062 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0004 ,  G11C15/02 ,  G11C15/04 ,  G11C15/046 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2207/063 ,  G11C2213/72 ,  G11C2213/79

摘要： The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

摘要翻译： 非易失性存储装置包括：电流检测电路，用于在数据检索操作中将存储单元行中以非易失性方式写入的存储信息与检索信息进行比较，以便确定存储信息是否与检索信息匹配 。 电流检测电路将流过与存储有存储信息的存储单元行的每个存储单元相对应的每个位线的数据读取电流与流过与存储检索信息的每个检索存储单元相对应的每个位线的数据读取电流进行比较。

公开(公告)号：US07072207B2

公开(公告)日：2006-07-04

申请号：US10777069

申请日：2004-02-13

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/14 ,  G11C11/00 ,  G11C5/08 ,  G11C8/00 ,  G11C8/02

CPC分类号： G11C7/12 ,  G11C11/15 ,  G11C11/16

摘要： For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

公开(公告)号：US07057925B2

公开(公告)日：2006-06-06

申请号：US11045100

申请日：2005-01-31

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/14

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

摘要： In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

公开(公告)号：US06999342B2

公开(公告)日：2006-02-14

申请号：US11119937

申请日：2005-05-03

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/14

CPC分类号： G11C14/0081

摘要： A power control unit activates a control signal ST for a circuit block to be set to a standby state before turning off power of the circuit block or a whole chip, and saves an operation result of data processing of the circuit block into a memory unit. When the power is again supplied to the circuit block in the standby state, the power control unit activates a control signal RES after the power supply is started and restores the data saved in the memory unit to the circuit block. Flip-flops in the circuit block are connected in series when the saving or restoring of data is performed, and perform a data transfer operation with a path different from that in a normal operation. Therefore, a semiconductor device can be provided which can rapidly transit to a standby mode having reduced current consumption while holding internal information.

摘要翻译： 功率控制单元在关闭电路块或整个芯片的电源之前激活用于待设置状态的电路块的控制信号ST，并将电路块的数据处理的操作结果保存到存储单元中。 当在待机状态下再次向电路块提供电源时，电源控制单元在电源启动之后激活控制信号RES，并将保存在存储器单元中的数据恢复到电路块。 当执行数据的保存或恢复时，电路块中的触发器串联连接，并且执行与正常操作不同的路径的数据传输操作。 因此，可以提供半导体器件，其可以在保持内部信息的同时快速转移到具有降低的电流消耗的待机模式。

公开(公告)号：US20060002216A1

公开(公告)日：2006-01-05

申请号：US11188089

申请日：2005-07-25

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C7/02

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

摘要： Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.

公开(公告)号：US20050270829A1

公开(公告)日：2005-12-08

申请号：US11145980

申请日：2005-06-07

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/21 ,  G11C11/15 ,  G11C29/00 ,  G11C29/04 ,  G11C11/00

CPC分类号： G11C15/046 ,  G11C11/16 ,  G11C13/0004 ,  G11C15/02 ,  G11C29/816 ,  G11C29/846

摘要： In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

摘要翻译： 在MRAM的存储单元阵列中，将正常存储单元与保持参考值的参考存储单元进行比较，从而存储每个单元一位的数据。 两个备用存储单元整体存储一位的数据。 通过将补充值写入两个备用存储单元并将这些备用存储单元连接到读出放大器，读取一位的存储数据。 经常布置在阵列周边部分中的备用存储单元部分变得更加抵抗元件的成品尺寸的变化，并且由备用存储单元更换和释放有缺陷的存储单元的成功率增加。

公开(公告)号：US20050195664A1

公开(公告)日：2005-09-08

申请号：US11119937

申请日：2005-05-03

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C14/00 ,  G11C7/00

CPC分类号： G11C14/0081

摘要： A power control unit activates a control signal ST for a circuit block to be set to a standby state before turning off power of the circuit block or a whole chip, and saves an operation result of data processing of the circuit block into a memory unit. When the power is again supplied to the circuit block in the standby state, the power control unit activates a control signal RES after the power supply is started and restores the data saved in the memory unit to the circuit block. Flip-flops in the circuit block are connected in series when the saving or restoring of data is performed, and perform a data transfer operation with a path different from that in a normal operation. Therefore, a semiconductor device can be provided which can rapidly transit to a standby mode having reduced current consumption while holding internal information.