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公开(公告)号：US20060092691A1
公开(公告)日：2006-05-04
申请号：US11264939
申请日：2005-11-02
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32
摘要： A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of the other side; the electrode 1 of one side in each element of the two variable resistance elements 11 and 12 is made a common electrode; and the electrode 2 of the other side in each element of the two variable resistance elements 11 and 12 is made independent and is provided respectively with the terminal X and terminal Y, to form a memory cell having two terminals in total.
摘要翻译： 具有可以容易地判断记录数据的内容并且能够降低功耗的配置的存储元件及其驱动方法。 本发明的存储元件10包括可变电阻元件11和12，其电阻状态在高电阻状态和低电阻状态之间可逆地改变，通过在一侧的电极1和电极2之间施加不同极性的电压 另一边; 将两个可变电阻元件11和12的每个元件中的一侧的电极1制成公共电极; 并且两个可变电阻元件11和12的每个元件中的另一侧的电极2被制成独立的并且分别设置有端子X和端子Y，以形成总共具有两个端子的存储单元。
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2.发明授权Two variable resistance elements being formed into a laminated layer with a common electrode and method of driving the same 有权两个可变电阻元件形成为具有公共电极的层压层及其驱动方法公开(公告)号：US07433220B2
公开(公告)日：2008-10-07
申请号：US11264939
申请日：2005-11-02
IPC分类号： G11C11/22
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32
摘要： A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of the other side; the electrode 1 of one side in each element of the two variable resistance elements 11 and 12 is made a common electrode; and the electrode 2 of the other side in each element of the two variable resistance elements 11 and 12 is made independent and is provided respectively with the terminal X and terminal Y, to form a memory cell having two terminals in total.
摘要翻译： 具有可以容易地判断记录数据的内容并且能够降低功耗的配置的存储元件及其驱动方法。 本发明的存储元件10包括可变电阻元件11和12，其电阻状态在高电阻状态和低电阻状态之间可逆地改变，通过在一侧的电极1和电极2之间施加不同极性的电压 另一边; 将两个可变电阻元件11和12的每个元件中的一侧的电极1制成公共电极; 并且两个可变电阻元件11和12的每个元件中的另一侧的电极2被制成独立的并且分别设置有端子X和端子Y，以形成总共具有两个端子的存储单元。
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公开(公告)号：US08369128B2
公开(公告)日：2013-02-05
申请号：US12747832
申请日：2008-12-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/79 , G11C2213/82
摘要： A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).
摘要翻译： 提供能够减少需要控制和减小外围电路尺寸的电压数量的存储装置。 第一脉冲电压（VBLR）从第一电源通过位线BLR提供给可变电阻元件的电极。 用于选择单元的第二脉冲电压（VWL）从第二电源通过字线WL提供给晶体管的控制端。 第三脉冲电压（VBLT）通过位线BLT从第三电源提供给晶体管的第二输入/输出端。 在重写信息时，通过调整电路来调整第三电源的电压值（VBLT）。 由此，电池电压和电池电流发生变化（减少或增加）。
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公开(公告)号：US20070247894A1
公开(公告)日：2007-10-25
申请号：US11738933
申请日：2007-04-23
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译： 提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。 存储装置包括由可变电阻元件形成的多个存储单元。 该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。
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公开(公告)号：US20120218809A1
公开(公告)日：2012-08-30
申请号：US13397282
申请日：2012-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/79
摘要： A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.
摘要翻译： 存储装置包括：多个存储元件，其被配置为根据施加的电压使其电阻状态发生变化; 以及驱动部，被配置为执行电阻变化操作和读取操作，所述电阻改变操作涉及通过改变其电阻状态来从存储元件写入或擦除信息，所述读取操作涉及从存储元件读取信息; 其特征在于，所述驱动部具有：放大器，被配置为在执行所述读取操作时输出读取信号;恒定电流负载;以及被配置为对所述存储元件执行电阻变化操作和直接验证操作的控制部，所述直接验证操作 涉及在电阻变化操作之后进行用于验证是否正常地完成对存储元件的写入或擦除信息的读取操作。
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公开(公告)号：US08213214B2
公开(公告)日：2012-07-03
申请号：US12747413
申请日：2008-12-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/56 , G11C2213/79
摘要： A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ΔVWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ΔVWL is a value variable for every resistance value level of multiple value information. That is, ΔVWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ΔVWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ΔVWL is large.
摘要翻译： 提供一种存储装置，其提高了在记录中调整电阻值电平的能力并且实现了稳定的验证控制。 通过WL调整电路的验证控制，每次重新录制时，从第二电源向晶体管的控制端子提供的VWL增加（增加部分：＆Dgr; VWL）。 在可变电阻元件能够记录多个值的情况下，＆Dgr; VWL是多值信息的每个电阻值电平的值变量。 也就是说，＆Dgr; VWL是根据由于电流引起的可变电阻元件的记录电阻的变化范围的大小关系的值变量。 在记录电阻的变化范围大（晶体管的源极栅极电压VGS小）的区域中，＆Dgr; VWL小，而在记录电阻的变化范围小（VGS大的区域） ），＆Dgr; VWL很大。
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7.发明授权Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权非易失性半导体存储器件及其执行验证写入操作的方法公开(公告)号：US08102716B2
公开(公告)日：2012-01-24
申请号：US12654783
申请日：2010-01-04
IPC分类号： G11C11/34
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译： 这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证 写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。
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8.发明申请Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权非易失性半导体存储器件及其执行验证写入操作的方法公开(公告)号：US20100195370A1
公开(公告)日：2010-08-05
申请号：US12654783
申请日：2010-01-04
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译： 这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证 写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。
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公开(公告)号：US08363447B2
公开(公告)日：2013-01-29
申请号：US12745952
申请日：2008-12-11
IPC分类号： G11C13/02
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/0011 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-bit recording is provided. An initial value of a potential difference VGS between a gate and a source of a switching transistor at the time of the verify is set to a value varied based on a resistance value level of multi-bit information. In the case of recording 2 bits when “01” is the information, an initial value VGS01 is set to be smaller than VGS=1.7 V corresponding to the target resistance value level “01”, and when “00” is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level “00” and higher than the above-described VGS01. This can reduce the number of cycles necessary for the verify process.
摘要翻译： 提供能够减少在多位记录时进行验证所需的循环次数的存储装置。 在验证时，开关晶体管的栅极和源极之间的电位差VGS的初始值被设定为基于多位信息的电阻值电平而变化的值。 在01是信息时记录2位的情况下，将初始值VGS01设定为小于对应于目标电阻值电平01的VGS = 1.7V，当00为信息时，将其设定为较低 比对应于目标电阻值电平00并高于上述VGS01的VGS = 2.2V。 这可以减少验证过程所需的周期数。
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公开(公告)号：US08446756B2
公开(公告)日：2013-05-21
申请号：US12671939
申请日：2008-08-12
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0092 , G11C2213/56 , H01L27/101 , H01L45/085 , H01L45/1266 , H01L45/146
摘要： Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.
摘要翻译： 提供一种驱动能够提高包括可变电阻元件的存储装置中的数据写入的可靠性的存储装置的方法。 在数据写入操作时，在可变电阻元件2中的电极21和24之间施加具有彼此不同形状的多个写入脉冲。由自发热引起的导电路径的扩散损耗（产生焦耳热 ）可以防止可变电阻元件2的数据保持操作。 此外，当充分执行写入操作时，可以防止可变电阻元件2被破坏，从而使数据写入操作稳定。
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