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公开(公告)号：US08446756B2
公开(公告)日：2013-05-21
申请号：US12671939
申请日：2008-08-12
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0092 , G11C2213/56 , H01L27/101 , H01L45/085 , H01L45/1266 , H01L45/146
摘要： Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24 in a variable resistance element 2. Diffusion loss of a conductive path caused by self-heat generation (generation of Joule heat) of the variable resistance element 2 may be prevented, and thus data hold operation after write is stabilized. Also, the variable resistance element 2 may be prevented from being destructed when the write operation is sufficiently performed, and thus the data write operation is stabilized.
摘要翻译： 提供一种驱动能够提高包括可变电阻元件的存储装置中的数据写入的可靠性的存储装置的方法。 在数据写入操作时，在可变电阻元件2中的电极21和24之间施加具有彼此不同形状的多个写入脉冲。由自发热引起的导电路径的扩散损耗（产生焦耳热 ）可以防止可变电阻元件2的数据保持操作。 此外，当充分执行写入操作时，可以防止可变电阻元件2被破坏，从而使数据写入操作稳定。
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公开(公告)号：US07583525B2
公开(公告)日：2009-09-01
申请号：US11738933
申请日：2007-04-23
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译： 提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。 存储装置包括由可变电阻元件形成的多个存储单元。 该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。
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公开(公告)号：US07221600B2
公开(公告)日：2007-05-22
申请号：US11186207
申请日：2005-07-21
申请人： Masaaki Hara , Nobumichi Okazaki
发明人： Masaaki Hara , Nobumichi Okazaki
CPC分类号： G11C11/22 , G11C11/223 , G11C13/0004 , G11C13/02 , G11C15/046
摘要： An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.
摘要翻译： 提供具有紧凑且高速的内存存储器的算术电路，其中执行各种操作。 算术电路包括具有可变电阻元件R的存储元件，其中电阻状态在一个电极和另一个电极之间施加具有不同极性的电压的高电阻状态和低电阻状态之间可逆地变化，并且至少 MRD，MRS，MW 1和MW 2的一个晶体管分别连接到存储元件的两端; 其中数据被存储在存储元件中，通过任何晶体管输入的外部数据X，W，Y 1和Y 2的操作是通过晶体管MRD，MRS向存储元件的每个端施加电位来执行的 ，MW 1和MW 2，并且从存储元件输出操作的结果。
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4.发明申请公开(公告)号：US20070041242A1
公开(公告)日：2007-02-22
申请号：US11501697
申请日：2006-08-10
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C13/0002 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C2013/0073
摘要： One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.
摘要翻译： 一个或串联的场效应晶体管彼此交叉耦合，非易失性可变电阻元件的第一端子连接到其存储节点，并且可变电阻元件的另一个端子连接到电源线，从而形成存储单元 。 通过控制提供给该电源线的电压，在关闭电源时，紧接着关闭电源之前的存储单元的数据被存储在其中。
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5.发明授权Composite storage circuit and semiconductor device having the same composite storage circuit 失效具有相同复合存储电路的复合存储电路和半导体器件公开(公告)号：US07130224B2
公开(公告)日：2006-10-31
申请号：US10522316
申请日：2003-07-22
IPC分类号： G11C7/06
CPC分类号： G11C14/0081 , G11C11/005 , G11C11/14
摘要： An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit.According to the present invention, in a compound storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and a semiconductor device including the compound storage circuit, a determination circuit for comparing first storage information stored in the volatile storage circuit with second storage information that has already been stored in the nonvolatile storage circuit when storage information stored in the volatile storage circuit is written into the nonvolatile storage circuit is provided, and the first storage information is written into the nonvolatile storage circuit only when the first storage information is not equal to the second storage information.
摘要翻译： 本发明的目的是提供一种复合存储电路，它包括一个存储电路，该存储电路包括一个彼此并联连接的易失性存储电路和一个非易失性存储电路，它被设置为能够通过存储信息 等于存储在易失性存储电路中的存储信息到非易失性存储电路中，复合存储电路能够降低功耗，以及包括复合存储电路的半导体器件。 根据本发明，在包括彼此并联连接的易失性存储电路和非易失性存储电路的复合存储电路和包括复合存储电路的半导体器件中，确定电路用于比较存储在易失性存储器 提供了当存储在易失性存储电路中的存储信息被写入非易失性存储电路时已经存储在非易失性存储电路中的具有第二存储信息的电路，并且仅当第一存储信息被写入非易失性存储电路时， 存储信息不等于第二存储信息。
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公开(公告)号：US20060067114A1
公开(公告)日：2006-03-30
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US20050105347A1
公开(公告)日：2005-05-19
申请号：US10503658
申请日：2003-02-07
IPC分类号： G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C29/00
CPC分类号： G11C11/16
摘要： A magnetic storage apparatus provided using ferromagnetic tunnel junction devices is constituted by forming the ferromagnetic tunnel junction device by laminating a fixed magnetization layer and a free magnetization layer on top and back surfaces of a tunnel barrier layer, respectively, wiring word lines in the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, and wiring bit lines in the direction orthogonal to the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, wherein two different memory states can be written in the ferromagnetic tunnel junction device by inverting the direction of the current flowing through the bit lines. At the time of writing in the ferromagnetic tunnel junction device, the direction of the current flowing through the word line is inverted in the same direction as or the opposite direction to the magnetization direction of the fixed magnetization layer.
摘要翻译： 使用铁磁隧道结装置提供的磁存储装置通过分别在隧道势垒层的顶表面和背表面上层叠固定磁化层和自由磁化层来形成铁磁隧道结装置，分别在磁化方向上布线字线 的铁磁隧道结装置的固定磁化层，以及在与铁磁隧道结装置的固定磁化层的磁化方向正交的方向上的布线位线，其中可以将两个不同的存储器状态写入铁磁隧道结装置 通过反转流过位线的电流的方向。 在铁磁隧道结装置中写入时，流过字线的电流的方向与固定磁化层的磁化方向相同或相反的方向反转。
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公开(公告)号：US07423902B2
公开(公告)日：2008-09-09
申请号：US11420290
申请日：2006-05-25
IPC分类号： G11C11/14
CPC分类号： G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/79
摘要： A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.
摘要翻译： 存储装置包括设置在矩阵中的存储单元。 存储单元各自包括存储元件，当第一阈值电平或更高的电信号被施加时，其电阻从较高状态变化到较低状态，并且当电信号为 施加极性与第一阈值或更高的电信号的极性不同的第二阈值电平，以及与存储元件串联连接的电路元件。 在将擦除电压施加到至少一个存储单元的状态下，当前正在进行擦除的存储单元中，在从应用经过预定时间之后，将擦除电压施加到至少一个存储单元，擦除是 接下来执行。
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公开(公告)号：US07372718B2
公开(公告)日：2008-05-13
申请号：US11243342
申请日：2005-10-04
申请人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
发明人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
摘要翻译： 存储装置包括存储元件，其具有使得其电阻值由于高于或等于施加的第一阈值信号的电信号而从高状态变为低状态的特性，并且从低状态改变为 作为高于或等于极性与施加的第一阈值信号的极性不同的第二阈值信号的电信号的结果的高状态; 以及电路元件，其与所述存储元件串联连接并用作负载，所述存储元件和所述电路元件形成存储单元，并且所述存储单元被布置成矩阵，其中所述电路元件的电阻值 当存储元件被读取时与存储元件被写入或擦除时的电阻值不同。
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公开(公告)号：US20070153564A1
公开(公告)日：2007-07-05
申请号：US11420290
申请日：2006-05-25
IPC分类号： G11C11/00
CPC分类号： G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/79
摘要： A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.
摘要翻译： 存储装置包括设置在矩阵中的存储单元。 存储单元各自包括存储元件，当第一阈值电平或更高的电信号被施加时，其电阻从较高状态变化到较低状态，并且当电信号为 施加极性与第一阈值或更高的电信号的极性不同的第二阈值电平，以及与存储元件串联连接的电路元件。 在将擦除电压施加到至少一个存储单元的状态下，当前正在进行擦除的存储单元中，在从应用经过预定时间之后，将擦除电压施加到至少一个存储单元，擦除是 接下来执行。
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