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公开(公告)号：US20070247894A1
公开(公告)日：2007-10-25
申请号：US11738933
申请日：2007-04-23
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译： 提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。 存储装置包括由可变电阻元件形成的多个存储单元。 该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。
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公开(公告)号：US07583525B2
公开(公告)日：2009-09-01
申请号：US11738933
申请日：2007-04-23
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译： 提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。 存储装置包括由可变电阻元件形成的多个存储单元。 该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。
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公开(公告)号：US07242606B2
公开(公告)日：2007-07-10
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US20060109316A1
公开(公告)日：2006-05-25
申请号：US11243342
申请日：2005-10-04
申请人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
发明人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
IPC分类号： B41J2/05
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
摘要翻译： 存储装置包括存储元件，其具有使得其电阻值由于高于或等于施加的第一阈值信号的电信号而从高状态变为低状态的特性，并且从低状态改变为 作为高于或等于极性与施加的第一阈值信号的极性不同的第二阈值信号的电信号的结果的高状态; 以及电路元件，其与所述存储元件串联连接并用作负载，所述存储元件和所述电路元件形成存储单元，并且所述存储单元被布置成矩阵，其中所述电路元件的电阻值 当存储元件被读取时与存储元件被写入或擦除时的电阻值不同。
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公开(公告)号：US20060067114A1
公开(公告)日：2006-03-30
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US07372718B2
公开(公告)日：2008-05-13
申请号：US11243342
申请日：2005-10-04
申请人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
发明人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
摘要翻译： 存储装置包括存储元件，其具有使得其电阻值由于高于或等于施加的第一阈值信号的电信号而从高状态变为低状态的特性，并且从低状态改变为 作为高于或等于极性与施加的第一阈值信号的极性不同的第二阈值信号的电信号的结果的高状态; 以及电路元件，其与所述存储元件串联连接并用作负载，所述存储元件和所述电路元件形成存储单元，并且所述存储单元被布置成矩阵，其中所述电路元件的电阻值 当存储元件被读取时与存储元件被写入或擦除时的电阻值不同。
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公开(公告)号：US07542335B2
公开(公告)日：2009-06-02
申请号：US10530271
申请日：2003-09-18
IPC分类号： G11C11/14
CPC分类号： H01L27/222
摘要： It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data.In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.
摘要翻译： 提供互补式磁存储装置的任务是通过精确地执行写入存储数据来提高可靠性。 因此，在本发明中，在第一铁磁隧道结元件和第二铁磁隧道结元件中分别存储相互相反的存储数据的互补型磁存储器件中，第一铁磁隧道结元件和第二铁磁 隧道结元件相邻地形成在半导体衬底上，第一写入线如线圈缠绕在第一铁磁隧道结元件周围，同时第二写入线缠绕在第二铁磁隧道结元件上，如线圈，另外， 第一写入线的卷绕方向和第二写入线的卷绕方向相反。
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公开(公告)号：US20060067106A1
公开(公告)日：2006-03-30
申请号：US11224856
申请日：2005-09-13
申请人： Hironobu Mori , Hidenari Hachino , Chieko Nakashima , Tsutomu Sagara , Nobumichi Okazaki , Hajime Nagao
发明人： Hironobu Mori , Hidenari Hachino , Chieko Nakashima , Tsutomu Sagara , Nobumichi Okazaki , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C11/22 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0066 , G11C2213/79
摘要： A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.
摘要翻译： 提出了一种存储装置，其包括：沿着行方向布置的源极线; 沿列方向布置的位线; 存储元件，其布置在所述源极线和所述位线的交叉点处; 写入电路，连接到所述位线的一个端子并向所述位线施加预定电压; 以及电压调整电路，其连接到最靠近所述位线的另一个端子的存储元件; 其中，所述电压调整电路将施加到位于最靠近所述位线的另一端子的存储元件的电压与设定电压进行比较，从而调整所述写入电路对所述位线施加的电压。
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9.发明授权Composite storage circuit and semiconductor device having the same composite storage circuit 失效具有相同复合存储电路的复合存储电路和半导体器件公开(公告)号：US07130224B2
公开(公告)日：2006-10-31
申请号：US10522316
申请日：2003-07-22
IPC分类号： G11C7/06
CPC分类号： G11C14/0081 , G11C11/005 , G11C11/14
摘要： An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit.According to the present invention, in a compound storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and a semiconductor device including the compound storage circuit, a determination circuit for comparing first storage information stored in the volatile storage circuit with second storage information that has already been stored in the nonvolatile storage circuit when storage information stored in the volatile storage circuit is written into the nonvolatile storage circuit is provided, and the first storage information is written into the nonvolatile storage circuit only when the first storage information is not equal to the second storage information.
摘要翻译： 本发明的目的是提供一种复合存储电路，它包括一个存储电路，该存储电路包括一个彼此并联连接的易失性存储电路和一个非易失性存储电路，它被设置为能够通过存储信息 等于存储在易失性存储电路中的存储信息到非易失性存储电路中，复合存储电路能够降低功耗，以及包括复合存储电路的半导体器件。 根据本发明，在包括彼此并联连接的易失性存储电路和非易失性存储电路的复合存储电路和包括复合存储电路的半导体器件中，确定电路用于比较存储在易失性存储器 提供了当存储在易失性存储电路中的存储信息被写入非易失性存储电路时已经存储在非易失性存储电路中的具有第二存储信息的电路，并且仅当第一存储信息被写入非易失性存储电路时， 存储信息不等于第二存储信息。
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公开(公告)号：US07423902B2
公开(公告)日：2008-09-09
申请号：US11420290
申请日：2006-05-25
IPC分类号： G11C11/14
CPC分类号： G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/79
摘要： A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.
摘要翻译： 存储装置包括设置在矩阵中的存储单元。 存储单元各自包括存储元件，当第一阈值电平或更高的电信号被施加时，其电阻从较高状态变化到较低状态，并且当电信号为 施加极性与第一阈值或更高的电信号的极性不同的第二阈值电平，以及与存储元件串联连接的电路元件。 在将擦除电压施加到至少一个存储单元的状态下，当前正在进行擦除的存储单元中，在从应用经过预定时间之后，将擦除电压施加到至少一个存储单元，擦除是 接下来执行。
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