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1.发明授权SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect 有权SiGe器件采用SiGe嵌入式虚拟图案，可减轻微负载效应公开(公告)号：US07671469B2
公开(公告)日：2010-03-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L23/52
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译： 具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。 至少一个虚拟图案包含SiGe。
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2.发明申请SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT 有权具有用于识别微载荷效应的信号嵌入式模式的信号装置公开(公告)号：US20090166676A1
公开(公告)日：2009-07-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译： 具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。 至少一个虚拟图案包含SiGe。
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公开(公告)号：US20090261937A1
公开(公告)日：2009-10-22
申请号：US12493245
申请日：2009-06-29
申请人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
发明人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.
摘要翻译： 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。
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公开(公告)号：US20100252860A1
公开(公告)日：2010-10-07
申请号：US12420046
申请日：2009-04-07
申请人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
发明人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/423
摘要： A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
摘要翻译： 形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。
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公开(公告)号：US08860544B2
公开(公告)日：2014-10-14
申请号：US12493245
申请日：2009-06-29
申请人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
发明人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.
摘要翻译： 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。
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公开(公告)号：US07897995B2
公开(公告)日：2011-03-01
申请号：US12420046
申请日：2009-04-07
申请人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
发明人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/423
摘要： A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
摘要翻译： 形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。
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7.发明申请METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF 审中-公开将解耦电容器放入具有逻辑电路的半导体电路及其半导体电路的方法公开(公告)号：US20100065943A1
公开(公告)日：2010-03-18
申请号：US12211832
申请日：2008-09-17
IPC分类号： H01L27/04
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0811
摘要： A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor.
摘要翻译： 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同。
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公开(公告)号：US08587056B2
公开(公告)日：2013-11-19
申请号：US13419443
申请日：2012-03-14
申请人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
发明人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/4983 , H01L29/7833 , H01L29/7835
摘要： A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要翻译： 高压MOS晶体管包括覆盖半导体衬底的有源区的栅极; 漏极掺杂区域从栅极的边缘拉回距离L; 在栅极和漏极掺杂区域之间的第一轻掺杂区域; 第一离子阱中的源极掺杂区; 以及在栅极和源极掺杂区域之间的第二轻掺杂区域。
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公开(公告)号：US20100164018A1
公开(公告)日：2010-07-01
申请号：US12345676
申请日：2008-12-30
申请人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
发明人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/4983 , H01L29/7833 , H01L29/7835
摘要： A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要翻译： 高压MOS晶体管包括覆盖半导体衬底的有源区的栅极; 漏极掺杂区域从栅极的边缘拉回距离L; 在栅极和漏极掺杂区域之间的第一轻掺杂区域; 第一离子阱中的源极掺杂区; 以及在栅极和源极掺杂区域之间的第二轻掺杂区域。
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公开(公告)号：US20120168862A1
公开(公告)日：2012-07-05
申请号：US13419443
申请日：2012-03-14
申请人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
发明人： Ming-Cheng Lee , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/4983 , H01L29/7833 , H01L29/7835
摘要： A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要翻译： 高压MOS晶体管包括覆盖半导体衬底的有源区的栅极; 漏极掺杂区域从栅极的边缘拉回距离L; 在栅极和漏极掺杂区域之间的第一轻掺杂区域; 第一离子阱中的源极掺杂区; 以及在栅极和源极掺杂区域之间的第二轻掺杂区域。
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