公开(公告)号：US20010015462A1

公开(公告)日：2001-08-23

申请号：US09734771

申请日：2000-12-12

Applicant: U.S. Philips Corporation

Inventor： Martin J. Powell

IPC: H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L027/12

CPC classification number: H01L29/66757 ,  H01L21/28158 ,  H01L29/4908 ,  H01L29/66765

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract translation: 公开了一种制造薄膜晶体管（TFT）的方法，其包括由半导体沟道层连接的源电极和漏电极，由至少两个子层和栅电极形成的栅极绝缘层。 该方法包括以下步骤：通过使用薄膜技术沉积薄膜子层来形成栅极绝缘层; 以及通过印刷沉积印刷的子层，其中所述薄膜子层位于所述半导体沟道层附近。 TFT可以是顶栅TFT，其中薄膜子层形成在半导体沟道层上，并且其中印刷的子层形成在薄膜子层上。 或者，TFT可以是底栅TFT，其中印刷的子层形成在栅电极上; 其中所述薄膜子层形成在所述印刷的子层上，并且其中所述半导体沟道层形成在所述薄膜子层上。

公开(公告)号：US20010005598A1

公开(公告)日：2001-06-28

申请号：US09738920

申请日：2000-12-14

Applicant: U.S. Philips Corporation

Inventor： Martin J. Powell

IPC: H01L021/00

CPC classification number: G02F1/1368

Abstract: A method of manufacturing an active matrix device (10) comprising a row and column array of active elements wherein each element comprises a transparent pixel electrode (12) associated with a self-aligned, top gate transistor (14, R2) having a transparent gate electrode (26). The method comprising the steps of forming opaque source (22) and drain (22null) electrodes on a transparent substrate (51); forming a semiconductor channel layer (23) so as to join source (22) and drain (22null) electrodes; forming a gate insulating (24, 25) layer; and depositing a transparent conductive layer and forming both the transparent gate electrode (26) and the pixel electrode (32) therefrom. The transparent gate electrode (26) may be formed by depositing a layer of negative resist (52) over the transparent conductive layer, exposing the layer of negative resist through the substrate such that regions of the negative resist shadowed by the opaque electrodes (22, 22null) remain unexposed, removing the unexposed negative and, having masked the region (53) associated with the transparent pixel electrode (32), removing the exposed transparent conductive layer.

Abstract translation: 一种制造有源矩阵器件（10）的方法，包括有源元件的行和列阵列，其中每个元件包括与自对准的顶栅极晶体管（14，R2）相关联的透明像素电极（12），其具有透明栅极 电极（26）。 该方法包括在透明基板（51）上形成不透明源（22）和漏极（22'）电极的步骤; 形成半导体沟道层（23）以连接源极（22）和漏极（22'）电极; 形成栅极绝缘层（24,25）层; 以及沉积透明导电层并从其形成透明栅电极（26）和像素电极（32）。 透明栅极（26）可以通过在透明导电层上沉积一层负性抗蚀剂（52）而形成，通过衬底暴露负性抗蚀剂层，使得不可剥离电极（22,22）遮蔽阴性抗蚀剂的区域， 22'）保持未曝光，去除未曝光的负片，并且掩蔽与透明像素电极（32）相关联的区域（53），去除暴露的透明导电层。

公开(公告)号：US20020132401A1

公开(公告)日：2002-09-19

申请号：US10095872

申请日：2002-03-12

Applicant: U.S. PHILIPS CORPORATION

Inventor： Martin J. Powell

IPC: H01L021/00 ,  H01L021/84

CPC classification number: H01L29/66757 ,  H01L21/28158 ,  H01L29/4908 ,  H01L29/66765

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract translation: 公开了一种制造薄膜晶体管（TFT）的方法，其包括由半导体沟道层连接的源电极和漏电极，由至少两个子层和栅电极形成的栅极绝缘层。 该方法包括以下步骤：通过使用薄膜技术沉积薄膜子层来形成栅极绝缘层; 以及通过印刷沉积印刷的子层，其中所述薄膜子层位于所述半导体沟道层附近。 TFT可以是顶栅TFT，其中薄膜子层形成在半导体沟道层上，并且其中印刷的子层形成在薄膜子层上。 或者，TFT可以是底栅TFT，其中印刷的子层形成在栅电极上; 其中所述薄膜子层形成在所述印刷的子层上，并且其中所述半导体沟道层形成在所述薄膜子层上。

公开(公告)号：US20020084465A1

公开(公告)日：2002-07-04

申请号：US10055371

申请日：2002-01-23

Applicant: U.S. PHILIPS CORPORATION

Inventor： Peter W. Green ,  Martin J. Powell

IPC: H01L021/00

CPC classification number: H01L29/458 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765

Abstract: A method of forming a thin film transistor comprises providing first electrode layers (42) over a transparent substrate (40), the first electrode layers comprising a lower transparent layer (42a), and an upper opaque layer (42b). The first electrode layers are patterned to define a first electrode pattern in which an edge region of the transparent layer (42a) extends beyond an edge region of the opaque layer (42b). A transistor body region comprising a semiconductor layer (16) defining the channel area of the transistor and a gate insulator layer (18) is provided over the first electrode pattern (42). A transparent second electrode layer (46) is also provided. A negative resist (70) is exposed through the substrate (40), with regions of the negative resist layer (70) shadowed by the opaque layer (42b) of the first electrode pattern (42) remaining unexposed. These regions and the underlying second electrode layer (46) are removed to define a second electrode pattern which is substantially aligned with the opaque layer (42b) of the first electrode pattern (42). The method can be used for top or bottom gate TFTs and provides a self aligned gate structure with overlap between the source/drain and the gate, so that no additional processing of the semiconductor body is required.

Abstract translation: 形成薄膜晶体管的方法包括在透明衬底（40）上提供第一电极层（42），第一电极层包括下透明层（42a）和上不透明层（42b）。 图案化第一电极层以限定其中透明层（42a）的边缘区域延伸超过不透明层（42b）的边缘区域的第一电极图案。 包括限定晶体管的沟道区域的半导体层（16）和栅极绝缘体层（18）的晶体管体区域设置在第一电极图案（42）上。 还提供透明的第二电极层（46）。 负抗蚀剂（70）通过衬底（40）暴露，阴性抗蚀剂层（70）的区域被第一电极图案（42）的不透明层（42b）遮蔽，保持未曝光。 去除这些区域和下面的第二电极层（46）以限定与第一电极图案（42）的不透明层（42b）基本对齐的第二电极图案。 该方法可用于顶栅或底栅TFT，并提供在源极/漏极和栅极之间具有重叠的自对准栅极结构，使得不需要对半导体主体的附加处理。