公开(公告)号：US09978745B2

公开(公告)日：2018-05-22

申请号：US15289988

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

公开(公告)号：US11488870B2

公开(公告)日：2022-11-01

申请号：US16843880

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Hsieh ,  Kuan-Ti Wang ,  Han-Chen Chen ,  Kun-Hsien Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.

公开(公告)号：US20210287942A1

公开(公告)日：2021-09-16

申请号：US16843880

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Hsieh ,  Kuan-Ti Wang ,  Han-Chen Chen ,  Kun-Hsien Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L29/49 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.

公开(公告)号：US20180068998A1

公开(公告)日：2018-03-08

申请号：US15289988

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

公开(公告)号：US09853021B1

公开(公告)日：2017-12-26

申请号：US15614624

申请日：2017-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/49 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L27/0617 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.