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公开(公告)号:US20240222369A1
公开(公告)日:2024-07-04
申请号:US18098710
申请日:2023-01-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Wen Hung , Peng-Hsiu Chen , Su-Ming Hsieh , Ying-Ren Chen
CPC classification number: H01L27/0808 , H01L29/66174 , H01L29/93
Abstract: The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.
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公开(公告)号:US20240264224A1
公开(公告)日:2024-08-08
申请号:US18116272
申请日:2023-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Wen Hung , Jinn-Horng Lai , Yan-Zung Wang , Peng-Hsiu Chen , Su-Ming Hsieh
IPC: G01R31/28 , H01L23/485
CPC classification number: G01R31/2886 , H01L23/485
Abstract: A ground-signal-ground (GSG) device structure is provided in the present invention, including two signal pads aligned in a first direction and two ground pads respectively at two sides of each signal pad in a second direction, and two transmission lines between the two signal pads and are connected respectively with said two signal pads, and said two transmission lines extend toward each other in the first direction and connect to a device, wherein the two signal pads and the two transmission lines are only in the level of 7th metal layer or above in back-end-of-line (BEOL) metal layers.
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公开(公告)号:US20240243073A1
公开(公告)日:2024-07-18
申请号:US18116812
申请日:2023-03-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Wen Hung , Jinn-Horng Lai , Yan-Zung Wang , Peng-Hsiu Chen , Su-Ming Hsieh
IPC: H01L23/552 , H01L23/522
CPC classification number: H01L23/552 , H01L23/5225 , H01L2223/66
Abstract: A radio-frequency (RF) device includes a main device on a substrate, a first port extending along a first direction adjacent to a first side of the main device, a second port extending along the first direction adjacent to a second side of the main device, a first shield structure adjacent to a third side of the main device, a second shield structure adjacent to a fourth side of the main device, a first connecting structure extending along a second direction to connect the first port and the main device, and a second connecting structure extending along the second direction to connect the second port and the main device.
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公开(公告)号:US20240222355A1
公开(公告)日:2024-07-04
申请号:US18105888
申请日:2023-02-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Wen Hung , Peng-Hsiu Chen , Su-Ming Hsieh , Chun-Hsien Lin
IPC: H01L27/02 , H01L27/085 , H01L29/06 , H01L29/66 , H01L29/778
CPC classification number: H01L27/0207 , H01L27/085 , H01L29/0692 , H01L29/66462 , H01L29/7786
Abstract: The invention provides a layout pattern of a semiconductor cell, which comprises a substrate with a first L-shaped MESA region and a second L-shaped MESA region, wherein the shapes of the first L-shaped MESA region and the second L-shaped MESA region are mutually inverted by 180 degrees, a first high electron mobility transistor (HEMT) and a second high electron mobility transistor are located on the first L-shaped MESA region, and a third high electron mobility transistor and a fourth high electron mobility transistor are located on the second L-shaped MESA region.
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